Design of Logic Blocks for Efficient Architecture of FPGA

Abstract

This paper analyses different hybrid logic blocks composed of Look-Up Tables (LUTs) and Universal Logic Gates (ULGs). The pure LUT based architecture incurs a higher power or more area. A ULG is designed to realize efficient architecture than LUT based architectures. A hybrid logic block that contains a mixture of BLEs that has LUTs and HLEs with ULGs is the solution to achieve benefits including area, performance, and power. Various logic blocks with different ratios of BLEs and HLEs are analyzed and the performance is compared in terms of area, power and delay. The result shows that the designed logic block can save a tremendous amount of logic power along with delay improvement and logic area reduction.