A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs

Abstract

The main objective of the technique presented in this paper is to exploit the relations between a set of Boolean functions so as to generate one function from another. The paper defines a relation termed as split-equivalence between logical functions. Using this relation, a single look-up table (LUT) storing the truth table of a function F may be used to generate other functions that are split-equivalent to F resulting in an overall reduction in the logic area used to map the circuit on the FPGA. This paper proposes a new configurable logic block (CLB) architecture containing a single LUT that stores the truth table of a Boolean function F and is capable of generating three split-equivalent functions of F. Given a set of Boolean functions to be mapped onto LUTs, the technique proposed identifies sets of four functions such that any three of them are split-equivalent to the fourth. These sets are mapped on to the proposed CLB architecture. The proposed CLB architecture was compared with the standard CLBs available on Xilinx Virtex architecture and it was found that the former occupies 26% lesser area than the latter with a small increase in the SRAM configuration bits required to configure a CLB.