Exploring shared SRAM tables among NPN equivalent large LUTs in SRAM-based FPGAs

Abstract

In modern SRAM based Field Programmable Gate Arrays, a Look-Up Table (LUT) is the principal constituent logic element which can realize every possible Boolean function. However, this flexibility of LUTs comes with a heavy area penalty. A part of this area overhead comes from the increased amount of configuration memory which rises exponentially as the LUT size increases. To reduce the area as well as the number of configuration bits, we have further explored and improved a previously proposed novel FPGA architecture which allows sharing of LUTs memory tables among NPN equivalent functions. A recently proposed high performance Boolean matching algorithm has been employed to perform NPN classification. Furthermore, a new clustering technique has also been proposed which packs NPN equivalent functions together inside a Configurable Logic Block (CLB). Consequently, this work explores the SRAM-table sharing approach for a range of LUT sizes (4–7), while varying the cluster sizes (4–16). Experimental results on MCNC benchmark circuits set show an overall area reduction of ∼ 3.7% while maintaining the same critical path delay.