Logic algebra for exploiting shared SRAM-table based FPGAs for large LUT inputs

Abstract

Techniques to establish correspondence between two Boolean functions have been under study for several decades now. Boolean Matching is a methods employed frequently by researchers to analyze the equivalence among Boolean functions. In this article we have utilized the concept of Boolean Matching to reduce the number of configuration bits in an FPGA architecture which allows sharing of LUTs memory tables among NPN equivalent functions. A canonical form based high performance Boolean matching algorithm has been employed to perform NPN classification. Furthermore, a new clustering technique has also been proposed which packs NPN equivalent functions together inside a Configurable Logic Block (CLB). By using CLBs with shared LUTs, the configuration memory cells of logic blocks were reduced by ∼ 30% which resulted in area savings of up to ∼ 3.7%, with a negligible penalty on the critical path delay (< 1%).