Concurrent Error Detection Research Articles

Design of Self–Checking Digital Devices with Boolean Signals Correction Using Weight-Based Bose–Lin Codes

This paper proposes a method for designing self-checking digital devices with Boolean signals correction and weight-based Bose–Lin codes. Unlike previous studies, the method involves Boolean signals correction (BSC) in the concurrent error-detection (CED) circuit for those functions describing the outputs of source devices that participate in the formation of data symbols of weight-based Bose–Lin codes. In such codes, as in the absolute majority of uniform separable codes, several data vectors correspond to the same check vector; therefore, it is possible to choose a method for determining BSC functions. We describe an algorithm for determining their values for each input combination, considering the testability of the checker and transformation elements in the CED circuit. The method involves the so-called “base” structure for monitoring multi-output devices by output groups. With this method, the designer of a self-checking device has high variability in choosing the design method and can regulate important indicators (structure redundancy, controllability, energy consumption, and others). Experiments with combinational benchmarks from MCNC Benchmarks were carried out. According to the experimental data, the method has high efficiency in terms of structure redundancy compared to the duplication method widespread in practice. The method can be effective when designing real devices with fault detection used in all areas of technology, including critical application systems in industry and transport.

Self-Checking Combinational Devices Synthesis Based on the Boolean Signal Correction Method Using Bose—Lin Codes

An organizing concurrent error-detection (CED) circuit new method for automation and computer technology combinational device is considered. The method based on the signal's Boolean correction method. The author proposed to use separable codes in the CED circuit synthesis when converting values from all operational outputs of the diagnosing object. The proposed approach allows to consider many possible transformations for each input combination. In addition, it will allow to choose the transformations to provide the conditions for building a completely self-checking device. In comparison with the methods previously discussed in the literature, the proposed approach makes it possible to synthesize a large number of control logic devices in the CED circuit and choose the most appropriate option. For example, with the technical implementation complexity lowest indicators. An algorithm for synthesizing the control logic block is given on the example of using a separable Bose — Lin code with module M = 4 by the signals Boolean correction method when organizing an CED circuit. The proposed method advantages and disadvantages for the CED circuit synthesis are described.

Efficiency Analysis of Concurrent Error-Detection Circuits on the Basis of Assessment by Belonging of Calculated Functions to Self-Dual Class and Preliminary Compression of Signals Using Linear Codes

A method is described for checking of calculations on whether functions belong to the class of self-dual with using well-known linear codes for preliminary compression of signals from the outputs of combinational devices in order to reduce the number of controlled signals. A generalized structure for organizing the checking of calculations with signal compression using arbitrary separable codes is proposed, which complements the well-known structures of self-dual check of parity calculations («self-dual parity») and self-dual check with duplication of each function («self-dual duplication))). In the concurrent error-detection circuit according to the presented method, all devices, except for the self-dual complement block, are standardized (typical). Therefore, to synthesize the concurrent error-detection circuit, it is necessary to obtain only the structure of this block in the selected elemental basis. The article presents a technique for synthesizing a block of self-dual complement when organizing the checking of calculations using arbitrary separable codes. Examples of the implementation of devices with concurrent error-detection circuits based on well-known linear codes — parity codes, Hamming codes and their modifications are given. Some results of mod­eling devices with concurrent error-detection circuits are given, noting the advantages and disadvantages of using each of the codes considered. The results obtained in the study can be applied in the development of self-checking computing devices and systems.

Modified Hamming Codes in Computing Devices Technical Diagnostic Systems

Previously unknown error detection characteristics by types and multiplicities in modified Hamming codes code words are established. The rules for constructing this modification of Hamming codes are described. Detailed characteristic tables of codes with data vectors lengths m = 4...16 are given. The considered code's error detection properties brief analysis is given. The results obtained in the study can be effectively used in the digital computing devices with controllable structures synthesis, as well as in the self-checking concurrent error-detection (CED) circuit synthesis using the Boolean complement method. The modified Hamming codes key property is the impossibility of 100 % double error detection in all code word bits when any single and double errors that occur only in data bits are detected. That is why it is recommended, when synthesizing a CED circuit using the Boolean complement method, to convert only those functions that describe the operating functions of the diagnostic object that will form the modified Hamming code control bits, and to separate the converted and non-convertible outputs into two groups of independent outputs. The experiment results with test combinational circuits presented in the article confirm the effectiveness of their use in the CED circuit synthesis by the Boolean complement method.

Application of Codes with Low Multiplicity Errors Efficient Detection for the Concurrent Error-Detection Circuit Synthesis by the Boolean Complement Method

The article proposed to synthesize concurrent error-detection circuit (CED) by the Boolean complement method using systematic codes with efficient error detection in the low multiplicity. The classical and modified Hamming's codes using is considered. The code choice features in the CED organization by the Boolean complement method are described. The CED organization structures by the Boolean addition method are given, considering the properties off Hamming code and their modifications. The generalized algorithm implementation for the CED synthesis by the Boolean complement method using Hamming codes and their modifications is formulated. The procedure effectiveness examples for synthesizing the CED according to the proposed methods in comparison with the use of the classical duplication method are given.

Beware of Insufficient Redundancy

Fault injection attacks pose a serious threat to cryptographic implementations. Countermeasures beyond sensors and shields usually deploy some form of redundancy to detect or even correct errors. A few years ago, a novel design methodology called Impeccable Circuits has been introduced on how to correctly integrate Concurrent Error Detection (CED) schemes, based on Error-Detection Codes (EDCs), into cryptographic hardware circuits. The underlying adversary model limits attackers to inject at most t single-bit faults. By additionally considering the propagation of faults in combinational circuits, the countermeasure guarantees detection of any faulty computation caused by up to t single-bit faults.In this work, we present an experimental analysis of the Impeccable Circuits countermeasure and its underlying assumptions in modern semiconductor technology. More precisely, we have taken hardware implementations of the lightweight block cipher SKINNY equipped with various forms of the EDC-based CED schemes and realized them as cryptographic co-processors on a 40nm ASIC to experimentally evaluate their resistance to Laser Fault Injection (LFI) attacks. In short, our results show that it is fairly simple to overcome the protection offered by the integrated countermeasures when the length of the code n is smaller than twice its rank k (i.e., no full redundancy). This is not caused by any flaw in the underlying design methodology or concept, but merely demonstrates how easily the defined adversary model can be overcome. In our case, a standard black-box scan over the target using a common single-shot LFI setup is sufficient to occasionally inject more single-bit faults than those bounded by the underlying adversary model when n < 2k. The probability of such events proved to be large enough to perform successful key-recovery attacks via Differential Fault Analysis (DFA) in a matter of hours. Thus, we caution against limiting the redundancy in code-based FI countermeasures to less than the number of bits per word, especially in nanometer technologies, and point out that less-complex countermeasures like duplication showed a higher level of resistance in our experiments at a lower cost.

Dickson basis multiplier with concurrent error detection against fault attacks for lightweight cryptosystems

Fault attacks have been proved for efficiently breaking hardware-based elliptic curve cryptosystems. One way for fighting against fault attacks is to design the core multiplier circuit of elliptic curve cryptosystem with concurrent error detection capability. The multiplier with concurrent error detection only outputs its results if no existing error is found. This paper will design a systolic array Dickson basis multiplier with concurrent error detection capability for resisting fault attacks on elliptic curve cryptosystems.

Transitions weight-based sum code for the digital computing devices synthesis

A method for constructing a family of sum codes is described based on weighting the transitions between groups of bits in the data vector. In this case, weights are used that are powers of the number 2. This makes it possible to obtain a code with check bits described by linear functions. The proposed weight-based sum code makes it possible to synthesize self-checking devices based on the standard elements and optimization methods of the logical device’s structures. A standard structure of a device with a concurrent error-detection (CED) circuit based on transitions weight-based sum codes between bits groups in the data vector is presented. The standard structure advantage lies in the possibility of synthesizing CED circuits with technical implementation reduced complexity by using codes with check bits numbers that are much smaller than the data bits numbers. Self-checking devices synthesized using the described codes in some cases may turn out to be less redundant than when using the standard duplication structure. The structure disadvantage is the need to consider the restrictions on the multiplicity of errors arising at the outputs of the diagnostic objects. This limitation increases with a decrease in the number of check bits. Despite this, in many cases, the use of a standard structure based on transitions weight-based sum code between groups of digits in the data vector makes it possible to synthesize self-checking digital devices. Using a standard structure for organizing a CED circuit allows going to implement of fault-tolerant digital devices according to standard structures, one of which is given in this article.

Stress-Aware Periodic Test of Interconnects

Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.

Fault-tolerant Structures of Digital Devices Based on Boolean Complement with the Calculations Checking by Sum Codes

The article considers the construction of fault-tolerant digital devices and computing systems that does not use the principles of introducing modular redundancy. To correct the signals, a special distorted signal fixation unit, concurrent error-detection by the pre-selected redundant code circuit, as well as a signal correction block are used. The distorted signal fixation unit is implemented by the Boolean complement method, which makes it possible to design a large number of such blocks with different indicators of technical implementation complexity. When synthesizing a fault-tolerant device according to the proposed method, it is possible to organize a concurrent error-detection circuit for both the source device and the Boolean complement block in the structure of the distorted signal fixation unit. This makes it possible to choose among the variety of ways to implement fault-tolerant devices according to the proposed method, one that gives a device with the least structural redundancy. Various redundant codes can be used to organize concurrent error-detection circuits, including classical and modified sum codes. The author provides algorithms for the synthesis of distorted signal fixation unit and the Boolean complement block. The results of experimental researches with combinational benchmarks devices from the well-known LG’91 and MCNC Benchmarks sets are highlighted. The article presents the possibilities of the considered method for the organization of faulttolerant digital devices and computing systems.

Concurrent fault detection and location with minimal overhead in Ling parallel prefix adders with a scheme for fault tolerant Ling prefix adders

In this paper a scheme for concurrent error detection (CED) in Ling parallel prefix adders is put forth leveraging the even-odd independence inherent in this class of adders. The proposed technique is based on the simplest form of fault detection i.e. duplicating and comparing results. This is achieved utilizing the unique even-odd independence feature in the Ling prefix structure. This feature is exploited to implement the fault tolerant Ling prefix adder with minimum overhead.The area and power overhead for CED are examined and results show that they reduce as the word size increases with the area overhead going down to less than 10% and power overhead to about 13% for a 64-bit adder. Delay is extraneous as the normal adder operation is not affected due to CED. The proposed fault tolerant adder design is compared with earlier schemes and results show that the proposed design gives an improvement of about 30% in area, 10% in PDP and about 40% in the ADP. Cadence Incisive Unified Simulator v6.1 is used for the functional simulation. Detailed analysis of the performance has been carried out at TSMC 180 nm process node (slow-normal library) using Cadence RTL compiler v7.1. Hardware synthesis has been performed to compute the metrics area, power and delay.

The Concurrent Error-Detection Systems Organization Based on the Boolean Complement Method with the Preliminary Transformation of Operating Functions into Check Vectors of Berger Codes

The article describes a new way of concurrent error-detection (CED) systems organization using the Boolean complement method, which involves the use of pre-compression of signals from the diagnostic object using encoders of classical sum codes (Berger codes). Control of compressed signals is carried out using the constant-weight "1-out-of-4" code. In comparison with the known methods of the CED systems organization, it is possible to implement a self-checking digital device using one such circuit, and this significantly reduces the structural redundancy. The article suggests using the encoders of modified Berger codes with improved error detection characteristics as a compression scheme.

The Self-Checking Concurrent Error-Detection Systems Synthesis Based on the Boolean Complement to the Bose-Lin Codes with the Modulo Value M=4

The presented paper is devoted to the development of the Boolean complement method for the organization of the self-checking concurrent error-detection (CED) systems for digital devices. The article considers the features of using the modular sum codes (Bose-Lin codes) for these purposes, especially the Bose-Lin code by the modulo M = 4. This code has two check bits and only four different check vectors, this makes it easier to use it in the organization of the self-checking CED system. The article presents the block diagrams of the organization of the CED system by the method of Boolean complement to the considered modular sum code. The examples of the CED system synthesis by the Boolean complement method are given. The article defines the restrictions imposed on the CED systems synthesis procedure, and also forms an algorithm for synthesizing a self-checking CED systems by the method of the Boolean complement to the Bose-Lin code by the modulo M = 4.

(M+1)-Sequence Generators with Concurrent Error Detection

The paper proposes a method for designing self-checking pseudorandom number generators based on shift registers with linear and nonlinear feedbacks (LFSR and NLFSR, respectively). The concept of an (M + 1)-sequence generator is introduced for NLFSRs, which form sequences of the maximum possible length for a given generator bit width. The circuits of generators of (M – 1)- and (M – 3)-sequences have been modified in order to increase the length of the period of the generated sequences. Logical schemes of NLFSR self-control based on parity checking of PRNG states are presented.

КОДЫ БЕРГЕРА В СХЕМАХ ВСТРОЕННОГО КОНТРОЛЯ, РЕАЛИЗОВАННЫХ НА ОСНОВЕ МЕТОДА ЛОГИЧЕСКОГО ДОПОЛНЕНИЯ

The article deals with the previously unknown characteristics of the error detection by using classical Berger codes based on their multiplicities and types (unidirectional, symmetrical and asymmetrical), which can be applied in the concurrent error-detection (CED) systems synthesis, for example, through the use of Boolean complement method. The article shows that Berger codes do not detect a certain amount of both symmetrical, unidirectional and asymmetrical errors in code words. This differs from the previously identified characteristics of the error detection only in data vectors of Berger codes (in this case, any symmetrical errors are not detected, and any unidirectional and asymmetrical errors are detected, which is used in the synthesis of systems with fault detection). The share of undetectable er-rors from their total number for Berger codes with data vector lengths r = 4,…,7 is less than 2%, and for Berger codes with data vector lengths r = 8,…,15 it is less than 0.5%. The use of classical sum codes is effective in the CED systems synthesis, including the Boolean complement method, in which both data and check bits of code words are calculated using the diagnostic object itself

The features of the concurrent error-detection systems of combinational logic circuits based on the search for groups of symmetrically-independent outputs construction

The authors of the article found that in the use of classical sum codes (Berger codes) and a some of their modifications in the combinational circuits testing organization it is possible to detect both unidirectional and part of non-unidirectional errors in the data vectors. It is shown that it is possible to search for such groups of outputs of combinational circuits where only symmetrical errors occur due to stuck at-faults of elements of the internal structure of the circuits. Such groups of outputs are designated as symmetrically-independent outputs (SI-groups of outputs). The conditions of belonging of the group of outputs of the combinational circuits to the SI-groups of outputs are determined. It is shown that each SI-group of outputs can be controlled using a separate testing subsystem based on the code with the detection of any non-symmetrical errors (in particular, and any non-symmetrical errors up to certain multiplicities). The ways of searching for SI-groups of outputs in the combinational circuits testing organization are presented

Improved error detection performance of logic implication checking in FPGA circuits

Increased feature scaling to achieve high performance of miniaturized circuits has increased concerns related to their reliability as smaller circuits age faster. This means that more computational errors due to defects are expected in modern nanoscale circuits. Logic implication checking is a concurrent error detection technique that can detect a partial number of these errors at reduced hardware costs. However, implications-based error detection suffers from a low error coverage in FPGA-implemented circuits making it useless for any practical purposes. In this paper, we identify the reasons for a degraded performance of implication checking in FPGAs and propose multi-wire implications towards achieving better error detection probabilities (Pdetection). The addition of multi-wire implications boosts the number of candidate implications and contributes more valuable implications thereby increasing the average Pdetection achieved by almost 1.7 times at around 65.7% with only a 25% increase in the average area overhead for the given test circuits. Moreover, we show that the efficiency of implications in detecting errors not only varies from one circuit to another but that it also depends largely on the specific implementation of the circuit under test as supported through analytic analyses and comparisons between experimental results obtained from hardware fault injection of the implemented circuits and fault simulations on corresponding circuit netlists.

Fault diagnosis architecture for SKINNY family of block ciphers

Cryptographic hardware and software applications are prone to various attacks either from the environments or from the attacker to gain the secret key. Resource-constrained devices use lightweight cryptographic algorithms to achieve a high level of security. It's always a trade-off between efficient resource utilization and level of security. Out of different attacks, in recent years, fault injection attacks is well matured. It becomes imperative to choose the best and efficient fault diagnosis schemes for lightweight cryptography. In this paper, we propose novel Concurrent error detection (CED), i.e., recomputing with inverted operands (REIO) method for SKINNY Family of Block Ciphers to increase the reliability. The proposed fault detection technique for SKINNY round-based pipelined architecture is adapted. The result shows that the throughput overhead of the SKINNY remains within 2.5% variance for the proposed novel fault detection with a pipelined technique, a maximum of 10% area overhead. We have implemented the proposed fault detection scheme using Xilinx FPGA. Best to our knowledge, there is no CED based fault detection technique proposed in the literature for the SKINNY family of block ciphers. The implementation results show that the proposed scheme is more effective and well suited for resource-constrained environments.

Метод функционального контроля комбинационных логических устройств на основе самодвойственного дополнения до равновесных кодов

Метод функционального контроля комбинационных логических устройств на основе самодвойственного дополнения до равновесных кодов

Impeccable Circuits

By injecting faults, active physical attacks pose serious threats to cryptographic hardware where Concurrent Error Detection (CED) schemes are promising countermeasures. They are usually based on an Error-Detecting Code (EDC) which enables detecting certain injected faults depending on the specification of the underlying code. Here, we propose a methodology to enable correct, practical, and robust implementation of code-based CEDs. We show that straightforward hardware implementations of given code-based CEDs can suffer from severe vulnerabilities, not providing the desired protection level. In particular, propagation of faults into combinatorial logic is often ignored in security evaluation of these schemes. First, we formally define this detrimental effect and demonstrate its destructive impact. Second, we introduce an implementation strategy to limit the fault propagation effect. Third, in contrast to many other works where the fault coverage is the main focus, we present a detailed implementation strategy which can guarantee the detection of any fault covered by the underlying EDC. This holds for any time of the computation and any location in the circuit, both in data processing and control unit. In short, we provide practical guidelines how to construct efficient CED schemes with arbitrary EDCs to achieve the desired protection level. We practically evaluate the efficiency of our methodology by case studies covering different symmetric block ciphers and various linear EDCs.