Concurrent Error Correction Research Articles

On concurrent multiple error diagnosability in linear analog circuits using continuous checksum

Although most of the work done in fault tolerance is in the digital field, it is widely understood that error detection and correction capability in analog circuits has the same importance as in digital circuits. The technique proposed by Abhijit Chatterjee can realize concurrent single error detection and correction in linear analog circuits well. Based on his work, this paper addresses concurrent multiple error detection and correction in linear analog systems, which is known to be a difficult and unsolved problem. We prove that the concurrent error diagnosis scheme using continuous checksum can not be extended to the case of multiple errors under the assumption that the checker and the functional block will not fail simultaneously, though people are still attempting to make such an extension. © 1998 John Wiley & Sons, Ltd.

Fault-tolerant neural network with concurrent error detection and correction capability

Fault-tolerant neural network with concurrent error detection and correction capability

Fault-tolerant features in the HaL memory management unit

This paper describes fault-tolerant and error detection features in HaL's memory management unit (MMU). The proposed fault-tolerant features allow recovery from transient errors in the MMU. It is shown that these features were natural choices considering the architectural and implementation constraints in the MMU's design environment. Three concurrent error detection and correction methods employed in address translation and coherence tables in the MMU are described. Virtually-indexed and virtually-tagged cache architecture is exploited to provide an almost fault-secure hardware coherence mechanism in the MMU, with very small performance overhead (less than 0.01% in the instruction throughput). Low overhead linear polynomial codes have been chosen in these designs to minimize both the hardware and software instrumentation impact. >

On concurrent error location and correction of FFT networks

Fault tolerance has been one of the major issues for the VLSI based FFT networks. In this paper, two efficient approaches for concurrent error location and correction of FFT networks are proposed. Using our approach, a faulty component can be located at an additional try followed by log/sub 2/m comparisons of m corrupted outputs. An error can also be corrected, once it is detected, at a small modification of basic module with an additional try. Moreover, our approaches are general in the sense that they can be implemented with any concurrent error detection scheme employing a checksum approach for FFT networks.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Concurrent error detection and correction in real-time systolic sorting arrays

A novel approach to online error detection and correction for high-throughput VLSI sorting arrays is presented. The error model is defined at the sorting element level and both functional errors and data errors are considered. Functional errors are detected and corrected by exploiting inherent properties as well as newly discovered special properties of the sorting array. Coding techniques are used to locate data errors. All the checkers are designed to be totally self-checking and hence the sorting array is highly reliable. Two-level pipelining is employed, making the design very efficient and suitable for real-time application. The structure is very regular and therefore is very attractive for VLSI or WSI implementation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A reconfigurable parallel signature analyzer for concurrent error correction in DRAM

An efficient strategy for utilizing a parallel signature analyzer (PSA) for concurrent soft-error correction in DRAMs (dynamic random-access memories) is described. For a two-level w-bit, n-word memory system, the proposed technique needs only one additional chip as opposed to log/sub 2/w+2 in the conventional Hamming code. Such an error-correction circuit significantly improves the reliability of the memory system. >

Implementation of 32-bit RISC processor incorporating hardware concurrent error detection and correction

The need for reliable integrated circuits is becoming of paramount importance as they are increasingly used in a range of safety critical applications or domestic products. In the past reliability has been achieved at the IC level by comprehensive testing of the device after manufacture. The use of scan design and BILBO techniques have assisted designers in achieving the necessary high test coverages with little effort. However these methods only address the problem of testing for permanent faults after fabrication or periodically during the lifetime of a system. These ‘classical’ techniques do not tackle the more serious problem of intermittent faults, which will come to dominate VLSI circuits as device geometries decrease. To deal with intermittent faults and maintain reliable operation concurrent test methods need to be used. The paper will present one possible method of detecting and correcting single intermittent faults that occur during normal operation and also assist the designer in post fabrication testing. The chosen technique uses information redundancy in the form of a SEC/DED Hamming code and will be illustrated by the design of a 32-bit CMOS RISC processor. The processor is capable of detecting and correcting errors arising from faults as they occur without the need to halt normal operations or recourse to any specialised software. A detailed appraisal of the costs involved in using this technique will be given in terms of the extra silicon area needed and the reduction in throughput of the processor.

Local concurrent error detection and correction in data structures using virtual backpointers

Two linked data structures utilizing virtual backpointers, the virtual double-linked list (VDLL) and the B-tree with virtual backpointers (VBT), are described. Four experiments that provide example measurements of the capabilities (behavior under multiple error conditions) and performance (time overhead) of both local concurrent error detection and correction using sample VDLL and VBT instances are described. For these structures, double errors within a fixed-size checking window can be detected in constant time, and single errors detected during forward moves can be corrected in constant time.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Concurrent error correction in systolic architectures

It is shown how two features of systolic arrays in which the cells retain partial results rather than pass them on can be used to facilitate testing and fault localization with no modification of the systolic design; the monitoring is performed either by software in the host processor or by hardware following the system output. One feature is the ability to enter identical sequences of inputs into two adjacent processor elements; the other is the resemblance of the data flow to that of a scan design. In particular, a one-dimensional systolic architecture of interest is described and applied to a finite-impulse response filter. Both the error detection and correction coverages are considered in detail for the FIR filter. The concurrent error-correction technique is applicable only to operational reliability, but the concurrent error-detection technique is equally applicable to manufacturing tests, incoming tests, and periodic maintenance tests. A hardware implementation of the error-detection-and-correction technique is presented. The architecture is extended to a two-dimensional processor. >

Concurrent error correction in unidirectional linear arrays

Abstract A concurrent error detection and correction algorithm for errors caused by permanent, intermittent and transient faults in a unidirectional linear array is introduced. The fault model we assumed here is based on some unknown reasons and may affect a small area of the IC chip. The structure based on this time‐redundant technique is proposed. The simplicity of the adding circuitry to a normal linear array makes this structure very attractive in VLSI implementation. The error‐correction capability and the total processing time for an n operands k stages processes are also discussed.