Implementation of 32-bit RISC processor incorporating hardware concurrent error detection and correction

Abstract

The need for reliable integrated circuits is becoming of paramount importance as they are increasingly used in a range of safety critical applications or domestic products. In the past reliability has been achieved at the IC level by comprehensive testing of the device after manufacture. The use of scan design and BILBO techniques have assisted designers in achieving the necessary high test coverages with little effort. However these methods only address the problem of testing for permanent faults after fabrication or periodically during the lifetime of a system. These ‘classical’ techniques do not tackle the more serious problem of intermittent faults, which will come to dominate VLSI circuits as device geometries decrease. To deal with intermittent faults and maintain reliable operation concurrent test methods need to be used. The paper will present one possible method of detecting and correcting single intermittent faults that occur during normal operation and also assist the designer in post fabrication testing. The chosen technique uses information redundancy in the form of a SEC/DED Hamming code and will be illustrated by the design of a 32-bit CMOS RISC processor. The processor is capable of detecting and correcting errors arising from faults as they occur without the need to halt normal operations or recourse to any specialised software. A detailed appraisal of the costs involved in using this technique will be given in terms of the extra silicon area needed and the reduction in throughput of the processor.