Abstract
Abstract A concurrent error detection and correction algorithm for errors caused by permanent, intermittent and transient faults in a unidirectional linear array is introduced. The fault model we assumed here is based on some unknown reasons and may affect a small area of the IC chip. The structure based on this time‐redundant technique is proposed. The simplicity of the adding circuitry to a normal linear array makes this structure very attractive in VLSI implementation. The error‐correction capability and the total processing time for an n operands k stages processes are also discussed.
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