Compressor Architecture Research Articles

Pulse compressor architecture to enable next-generation high-energy petawatt-class lasers

The maximum energy obtainable within a single aperture of a high-energy petawatt-class (HEPW) laser is typically limited by the pulse compressor. This work evaluates the potential impact of two new pulse compression grating technologies (HELD gratings and TM polarization) on HEPW laser systems. A compressor architecture is proposed that implements these grating advancements in order to support ∼6× higher pulse energies than currently demonstrated. This increase in energy and intensity could have substantial benefits to high-flux secondary sources and enable new applications.

Thermodynamic analysis of an enhanced ejector vapor injection refrigeration cycle for CO2 transcritical operation at low evaporating temperatures

The main drawback associated with CO2 refrigeration systems is related to their performance reduction during transcritical operation at warm climate conditions, which may be compensated by better cycle architectures such as the split-cycle with subcooling or the flash-tank configuration, among others. Specifically, the use of standard gas-ejectors together with parallel compressors provides even better efficiency improvements, not being able to use them with low-temperature evaporators to prevent the triple point inside the ejector. This paper proposes an enhanced cycle with a gas ejector for two-stage compressor architectures with vapor injection from the flash-tank, which is able to operate at low evaporating temperatures and that provides a greater performance improvement the more severe the climate conditions are. The methodology conducted is based on a thermodynamic analysis that includes parametric evaluation and cycle optimization, comparing the results to a conventional CO2 transcritical cycle with flash-tank and dynamic vapor injection architecture. The main results show that a maximum Coefficient of Performance improvement of 17.5% is achievable for transcritical operation at -40 °C evaporating temperature. The compressor displacement capacity required with the enhanced cycle is up to 9% lower for the same refrigeration demand, reducing the electrical consumption as well as the compressor expenditure. Moreover, greater vapor injection mass flow rates are obtained by the gas-ejector injection with discharge temperature reductions up to 18%, enhancing the system reliability.

Mechanistic chamber models: A review of geometry, mass flow, valve, and heat transfer sub-models

The evolution of computer resources paved the way for numerical models to substitute extensive experimental campaigns to develop and optimize compressors for the HVAC&R industry. A particular class of compressor models referred to as mechanistic (or deterministic) chamber model is well-known to be computationally efficient and has reasonable model fidelity for performance prediction and extrapolation. The overall model architecture requires inputs from various sub-models, including the mass flow, heat transfer and valve models. The accuracy of the overall model depends on the fidelity and accuracy of the individual sub-models. This article provides a comprehensive review of the different approaches available in literature which were used to model the geometry, mass flow, valves, and heat transfer processes in the compressor. The article aims to help researchers identify suitable approaches for their analysis. Additionally, it was found that there are opportunities for additional research to develop analytical correlations for discharge coefficients for the mass flow model, explore solubility in leakage gaps, develop effective flow/force area estimation for valve models, and develop instantaneous heat transfer coefficients for specific compressor architectures and thermal conductance models for multi-lumped network models.

Design and performance analysis of an ultra‐high‐speed 5‐2 compressor

AbstractA novel ultra‐high‐speed 5‐2 compressor is presented and discussed in this paper. The proposed structure is developed by modifying the truth table focusing on the carry rippling problem. By reducing the number of the states in the truth table and the complexity of the structure, the total delay is reduced while the power and active area are also improved. The proposed compressor is compared with the best recently reported ones where the designed architecture shows 9%–80% improvement in power delay product (PDP). For a better demonstration of the advantages, the proposed structure is placed in the body of a 16 × 16‐bit multiplier and is compared with the other multipliers consisting of the other 5‐2 compressor architectures. The results indicate an improvement equal to 13%. It must also be mentioned that the gate‐level delay calculation is emphasized in this paper, where a precise estimation method is utilized considering the capacitances at the middle‐stage nodes. Based on the calculations, the designed circuit has the minimum gate‐level delay compared to the other related works due to its minimal intermediate connections. For simulating the proposed structure, a standard CMOS 0.18‐μm process along with HSPICE software is used, where the results show a delay of 266.5 ps with a power consumption of 164 μw.

Development of a Reconfigurable Prototype Peristaltic Compressor

Traditional positive displacement compressors require valves, internal volume ratios or both to operate. These two features generate the majority of the losses in compressors. The peristaltic compressor is a novel compressor architecture that feature valve-less compression with variable volume ratios, which provides the potential for highly efficient compression. This paper will present a design of a reconfigurable prototype peristaltic compressor and illustrate how the structure of the compression chamber and actuation pattern affect the compressor efficiency. The prototype utilizes a flexible diaphragm constrained and sealed against a female die to make a compression chamber. Linear actuators with male dies press the diaphragm sequentially against the female die to move and compress the fluid. Preliminary experiments were performed using air as the working fluid for volume ratios ranging from 1.143 to 8 and operational frequencies ranging from 1.28 to 2.31 Hz. These results suggest that the actuation pattern has an impact on the major parameters such as mass flow, displacement volume, and pressure ratio which influence the overall efficiency of the compressor.

High Speed FIR Filter Using Radix-2r Multiplier and Its Application for Denoising EOG Signal

In this paper, a modified finite impulse response (FIR) filter design has been proposed for the denoising bio-electrical signals like Electrooculography(EOG). The proposed filter architecture uses modified multiplier block, which is implemented using modified Radix-[Formula: see text] arithmetic-based representation for minimizing the multiple constant multiplication and conventional ripple carry adders are replaced with [Formula: see text] compressors. This proposed architecture is implemented by using Radix-[Formula: see text]-based multiplier and [Formula: see text] compressor architectures for achieving better improvement in the critical path delay. The Radix-[Formula: see text]-based arithmetic bit recording is used in order to reduce the design complexity of the multiplication. The proposed architecture significantly reduced the delay when compared to existing and conventional architectures.

Designing a New 4:2 Compressor Using an Efficient Multi-Layer Full-Adder Based on Nanoscale Quantum-Dot Cellular Automata

Quantum-dot Cellular Automata (QCA) is novel prominent nanotechnology. It promises a substitution to Complementary Metal–Oxide–Semiconductor (CMOS) technology with a higher scale integration, smaller size, faster speed, higher switching frequency, and lower power consumption. It also causes digital circuits to be schematized with incredible velocity and density. The full adder, compressor, and multiplier circuits are the basic units in the QCA technology. Compressors are an important class of arithmetic circuits, and researchers can use quantum compressors in the structure of complex systems. In this paper, first, a novel three-input multi-layer full-adder in QCA technology is designed, and based on it, a new multi-layer 4:2 compressor is presented. The proposed QCA-based full-adder and compressor uses an XOR gate. The proposed design offers good performance regarding the delay, area size, and cell number comparing to the existing ones. Also, in this gate, the output signal is not enclosed, and we can use it easily. The accuracy of the suggested circuits has been assessed with the utilization of QCADesigner 2.0.3. The results show that the proposed 4:2 compressor architecture utilizes 75 cell and 1.25 clock phases, which are efficient than other designs.

Logically Optimal Novel 4:2 Compressor Architectures for High-Performance Applications

Multipliers are principal arithmetic components that play a key role in determining the performance of DSP architectures. While the efficiency of multipliers relies on optimal reduction of partial products within constraint power-delay values, this can be achieved by ‘compressors’ a precisely designed special arithmetic module. In this manuscript, authors propose low-power high-performance 4:2 compressor architectures. The presented designs perform better than the contemporary designs in terms of latency, improved power-delay and area-delay product values. The principal objective of this work is to design and develop a fast 4:2 compressor circuitry with optimal trade-off between power and area by pristine logical decomposition. All the referenced and proposed designs are simulated and synthesized in synopsys design compiler using prelayout CMOS standard cell library of TSMC 65 nm. From the synthesis results, it can be seen that the proposed model provides 12.5–29.17% reduction in area and 7–14.23% reduction in propagation delay with respect to state-of-the-art 4:2 compressor designs. In addition, to estimate the performance stability in realistic applications, 4-bit, 8-bit and 16-bit Dadda multiplier integrated with proposed compressor cells is implemented and verified. The obtained synthesis results substantiate that Dadda multiplier integrated with proposed compressor cells performs better than conventional and state-of-the-art 4:2 compressor-based variants with 4–8% reduction in propagation delay, upto 23.370% reduction in area-delay product and upto 25.62% reduction in power-delay product for 4-bit multiplication, while 6.77–16.85% reduction in propagation delay, 2.62–18.70% reduction in area-delay product and 15.30–23.20% reduction in power-delay product are achieved for 8-bit multiplication. For 16-bit multiplication it shows upto 47.05% reduction in propagation delay, upto 21.68% reduction in area-delay product and upto 24.42% reduction in power-delay product for 16-bit multiplication.

A modular Vedic multiplier architecture for model-based design and deployment on FPGA platforms

Multiplication is a fundamental operation in most signal and image processing applications. In this paper, a new architecture for a Vedic multiplier implementing ‘Urdhava-tiryakbhyam’ methodology is proposed. The presented architecture is completely modular and is conceived to be implemented in model-based designs where the configurability is of utmost importance. This architecture is prone to be implemented both as pure combinational and pipelined fashion to fit the needed frequency clock. The proposed multiplier exploits 4:2 compressor blocks instead of standard full-adders. Five different 4:2 compressor architectures from literature have been compared. The designs are developed as model-based schemes in SIMULINK and then automatically coded in VHDL (Very High-speed Integrated Circuits Hardware Description Language) through the HDL coder of MATLAB. The code is synthetized on an Artix 7 FPGA (Field Programmable Gate Array) and performances are evaluated in terms of area occupancy (i.e., LUTs number) and propagation delay (i.e., output time). Results show that despite the achieved configurability and modular architecture, the proposed solution performs equally or in some cases even better compared to solutions already presented in literature.

Novel Architecture for Low-Power CNTFET-Based Compressors

Carbon nanotube field-effect transistors (CNTFETs) are excellent candidates for the replacement of traditional CMOS circuits. One of the most important modules in many arithmetic circuits is multiplier. Sometimes multipliers may occupy more area as well as consume high power which may cause speed reduction in the critical path. Compressors are important building blocks which are used in most multipliers. In this paper, a low-power architecture is proposed which can be used in compressor designs. The proposed architecture uses a low-power three-input XOR gate to reduce area, delay and power consumption. In order to evaluate the delay and power consumption of circuits, we have used four different types of compressors (3–2, 4–2, 5–2 and 7–2). These four designs were simulated using HSPICE simulation tool with 32-nm CMOS model based on 1-V and 1-GHz frequency operator. The results indicate that the proposed compressor architectures have less power–delay product (PDP) and power consumption in comparison with the existing proposed compressors.

Performance Evaluation o f a n Efficient 5 2 Compressor f or Digital Applications

This paper presents an efficient performance 5-2 compressor which consumes less power. The architecture of this compressor consists of full adder, XOR’s, CGEN and MUX blocks. This architecture is mainly implemented based on Cout signals independent of Cin signals in order to reduce the carry propagation to a compressor. An efficient full adder is used to optimize the compressor architecture. In this design, an existing carry generator, XOR, MUX blocks configure with the proposed full adder circuit. The proposed design for full adder employs using pass transistor logic, which eliminates the weak logic in the circuit. This technique is mainly considerable for less power consumption. The parameters of proposed architecture is compared with other designs i.e. power-delay product, average-power, and delay. Simulations were done using HSPICE software in 130nm and 32nm technology. The simulation results show the improvement in the overall performance of the 5-2 compressor.

Fast Monolithic 8-2 Adder Compressor Circuit

Adder compressor architectures have been widely used in multipliers and have recently achieved improvements over conventional approaches in the computation of multiple modules, such as transform blocks, in the context of video coding. This paper reviews four different state-of-the-art 8-2 adder compressor architectures and proposes a novel one. A 65 nm commercial standard cell library was used to synthesize the compressors. The results show that, as a consequence of a shorter critical path, our circuit presented significant improvements regarding maximum operational frequency, while still maintaining similar results for power dissipation. Our circuit also managed to achieve a smaller circuit area, as a result of a more straightforward net interconnection.

Data Compression Device Based on Modified LZ4 Algorithm

Data compression is commonly used in NAND flash-based solid state drives (SSDs) to increase their storage performance and lifetime as it can reduce the amount of data written to and read from NAND flash memory. Software-based data compression reduces SSD performance significantly and, as such, hardware-based data compression designs are required. This paper studies the latest lossless data compression algorithm, i.e., the Lempel-Ziv (LZ)4 algorithm which is one of the fastest compression algorithms reported to date. A data compression FPGA prototype based on the LZ4 lossless compression algorithm is studied. The original LZ4 compression algorithm is modified for real-time hardware implementation. Two hardware architectures of the modified LZ4 algorithm (MLZ4) are proposed with both compressors and decompressors, which are implemented on an FPGA evaluation kit. The implementation results show that the proposed compressor architecture can achieve a high throughput of up to 1.92 Gb/s with a compression ratio of up to 2.05, which is higher than all previous LZ algorithm designs implemented on FPGAs. The compression device can be used in high-end SSDs to further increase their storage performance and lifetime.

Spatio-temporal modeling and optimization of a deformable-grating compressor for short high-energy laser pulses.

Monolithic large-scale diffraction gratings are desired to improve the performance of high-energy laser systems and scale them to higher energy, but the surface deformation of these diffraction gratings induce spatio-temporal coupling that is detrimental to the focusability and compressibility of the output pulse. A new deformable-grating-based pulse compressor architecture with optimized actuator positions has been designed to correct the spatial and temporal aberrations induced by grating wavefront errors. An integrated optical model has been built to analyze the effect of grating wavefront errors on the spatio-temporal performance of a compressor based on four deformable gratings. A 1.5-meter deformable grating has been optimized using an integrated finite-element-analysis and genetic-optimization model, leading to spatio-temporal performance similar to the baseline design with ideal gratings.

A Novel High Speed Full Adder Based on Linear Threshold Gate and its Application to a 4-2 Compressor

This paper proposes a novel full adder based on the linear threshold gate (LTG) which belongs to the single-electron-device (SED) family. The advantage of an LTG-based circuit is that it has a satisfactory fan-out as opposed to other SED-based circuits; hence, it can be utilized in any complex circuit network. The proposed full adder is utilized as an application in a 4-2 compressor architecture. Compressors are elementary building blocks which are widely used in arithmetic structures such as multipliers. The proposed 4-2 compressor can operate reliably in any tree structured parallel multiplier due to its high performance full adders. The SIMON simulator demonstrates the correct operation of the proposed full adder design, along with the presented 4-2 compressor. The performance of proposed full adder and the 4-2 compressor, in terms of delay and power consumption, are calculated in complete detail. The comparisons indicate that the proposed full adder has the highest speed in comparison with the previous high speed designs.

Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs

This paper presents the design of a soft IP for JPEG compression targeted for high performance in a FPGA device. The JPEG compressor architecture achieves high throughput with a deep and optimized pipeline and with a multiplierless datapath architecture. The JPEG compressor architecture was designed in a hierarchical and modular fashion and the details of the global architecture and of its modules are presented in this paper. A modular and strictly structural VHDL design is followed to develop the JPEG compressor soft IP. The VHDL codes were synthesized to Altera and Xilinx FPGAs. Synthesis results and relevant performance comparisons with related works are presented. Our high throughput compressor is able to compress 39.8 millions of pixels per second when mapped onto an Altera FLEX 10KE FPGA. Our JPEG soft IP mapped to FLEX 10KE low cost FPGA is able to compress 115 images per second in SDTV resolution (720 × 480 pixels). Considering this SDTV resolution our design is worthy as a core of an M-JPEG video compressor, reaching a real time processing rate of 30 fps, once mapped to the FLEX 10KE FPGA device.

High performance 5 : 2 compressor architectures

Fast arithmetic circuits are key elements of high performance computers and data processing systems. In the majority of these applications, multipliers have been a critical and obligatory component in dictating the overall circuit performance when constrained by power consumption and computation speed. Compressors are a critical component of the multiplier circuit, which greatly influence the overall multiplier speed. The authors propose two novel high performance 5 : 2 compressor architectures. The main objective of their designs is to limit the carry propagation to a single stage, thereby reducing the overall propagation delay. The designs are compared with the best one in the literature in terms of delay and are found to have lower values. The analytical techniques use the node capacitances in the signal delay paths to identify the worst delay path. The architectures are implemented with various XOR–XNOR circuits to identify the best one in terms of power and delay. The simulation results of the proposed architectures show lower power and 25% improvement in speed compared to the best architecture reported in the literature for supply voltages ranging from 1.5 V to 3.3 V.

Ultra Low-Voltage Low-Power CMOS 4-2 and 5-2 Compressors for Fast Arithmetic Circuits

This paper presents several architectures and designs of low-power 4-2 and 5-2 compressors capable of operating at ultra low supply voltages. These compressor architectures are anatomized into their constituent modules and different static logic styles based on the same deep submicrometer CMOS process model are used to realize them. Different configurations of each architecture, which include a number of novel 4-2 and 5-2 compressor designs, are prototyped and simulated to evaluate their performance in speed, power dissipation and power-delay product. The newly developed circuits are based on various configurations of the novel 5-2 compressor architecture with the new carry generator circuit, or existing architectures configured with the proposed circuit for the exclusive OR (XOR) and exclusive NOR ( XNOR) [XOR-XNOR] module. The proposed new circuit for the XOR-XNOR module eliminates the weak logic on the internal nodes of pass transistors with a pair of feedback PMOS-NMOS transistors. Driving capability has been considered in the design as well as in the simulation setup so that these 4-2 and 5-2 compressor cells can operate reliably in any tree structured parallel multiplier at very low supply voltages. Two new simulation environments are created to ensure that the performances reflect the realistic circuit operation in the system to which these cells are integrated. Simulation results show that the 4-2 compressor with the proposed XOR-XNOR module and the new fast 5-2 compressor architecture are able to function at supply voltage as low as 0.6 V, and outperform many other architectures including the classical CMOS logic compressors and variants of compressors constructed with various combinations of recently reported superior low-power logic cells.