Compression Architecture Research Articles

Compressive Channel Estimation and Tracking for Large Arrays in mm-Wave Picocells

We propose and investigate a compressive architecture for estimation and tracking of sparse spatial channels in millimeter (mm) wave picocellular networks. The base stations are equipped with antenna arrays with a large number of elements (which can fit within compact form factors because of the small carrier wavelength) and employ radio frequency (RF) beamforming, so that standard least squares adaptation techniques (which require access to individual antenna elements) are not applicable. We focus on the downlink, and show that "compressive beacons," transmitted using pseudorandom phase settings at the base station array, and compressively processed using pseudorandom phase settings at the mobile array, provide information sufficient for accurate estimation of the two-dimensional (2D) spatial frequencies associated with the directions of departure of the dominant rays from the base station, and the associated complex gains. This compressive approach is compatible with coarse phase-only control, and is based on a near-optimal sequential algorithm for frequency estimation which can exploit the geometric continuity of the channel across successive beaconing intervals to reduce the overhead to less than 1% even for very large (32 x 32) arrays. Compressive beaconing is essentially omnidirectional, and hence does not enjoy the SNR and spatial reuse benefits of beamforming obtained during data transmission. We therefore discuss system level design considerations for ensuring that the beacon SNR is sufficient for accurate channel estimation, and that inter-cell beacon interference is controlled by an appropriate reuse scheme.

Reconfigurable architecture for real-time image compression on-board satellites

Data products of optical remote sensing systems are increasingly used in many areas of our everyday life. The spatial as well as the spectral resolution of satellite image data increases steadily with new missions resulting in a higher precision of known procedures and new application scenarios. While the memory capacity requirements can still be fulfilled, the transmission capacity becomes increasingly problematic. Real-time transmission of high-resolution image data is currently not possible. This thesis presents a new image data compression architecture that can be used for current and future projects at the German Aerospace Center (DLR). The architecture has region-of-interest support and offers flexible access to the compressed data based on the CCSDS 122.0-B-1 image data compression standard. Region of interest (ROI) coding can be useful in scenarios where on-board classification, registration, or object or change detection algorithms are used. It is also useful to decrease the amount of data that must be transferred to the ground station. Modifications to the standard have been made to permit a change of compression parameters and the re-organization of the bit-stream after compression. An additional index of the compressed data is created, which makes it possible to locate individual parts of the bit-stream. On request, compressed and stored images can be re-assembled and transmitted according to the application's needs and as requested by the ground station. The requirements, the design of the architecture, and its implementation based on reconfigurable hardware are presented. The architecture was developed for a spacequalified Xilinx Virtex 5QV, where a single instance of the architecture is capable of compressing images at a rate of up to 200 Mpx/s (or 400 Mbyte/s for 16 bit images). It operates at a clock frequency of 100MHz and processes two image pixels per clock cycle. A Xilinx Virtex-5QV enables thereby compressing images with a width of up to 4096 pixels without the use of external memory. Without external memory and additional interfaces, the power consumption of the architecture is about 5 W. The proposed architecture is one of the fastest implementations yet reported and sufficient for recent high-resolution systems. Investigations in the resource and power consumption, as well as the availability of external storage have shown that it should be possible to integrate the design directly on a focal plane.

Low-Delay Parallel Architecture for Fractal Image Compression

This paper presents an efficient hardware architecture for implementing fractal image compression (FIC) algorithm aimed toward image compression with improved encoding speed. The proposed architecture follows the full-search-based FIC scheme. Parallel processing has been effectively used in the present work to achieve the goal of reducing the time complexity of the encoder. This architecture requires a total of $$2n+2$$2n+2 clock cycles for executing the set of operations consisting of fetching the pixels, calculating the mean of range and domain blocks and doing their mapping, computing the error, and storing the fractal parameter in a memory with n number of pixels in the range block. Further, this architecture does not make use of any preprocessing operations as specified in literature and utilizes the benefits of isometric transformation without requiring additional cycles for every single matching operation. Effective application of isometric transformation has also led to memory reduction of nearly 67 %. Again, in the present work, the use of multipliers has been avoided to save the chip area, to reduce hardware complexity, and to enhance the encoding speed. The operation of transforming contracted domain block with a zero-mean domain block has facilitated relatively fast convergence at the decoder. PSNR above 30dB for a range block of size $$4\times 4$$4×4 has been achieved by the proposed architecture, which is comparable to that realizable by other architectures. The proposed design has been coded in Verilog HDL, has been implemented in Xilinx Virtex-5 FPGA, and operates at a clock frequency of 75.52 MHz.

TEA: Timing and Energy Aware compression architecture for Efficient Configuration in CGRAs

Coarse Grained Reconfigurable Architectures (CGRAs) are emerging as enabling platforms to meet the high performance demanded by modern applications (e.g. 4G, CDMA, etc.). Recently proposed CGRAs offer time-multiplexing and dynamic applications parallelism to enhance device utilization and reduce energy consumption at the cost of additional memory (up to 50% area of the overall platform). To reduce the memory overheads, novel CGRAs employ either statistical compression, intermediate compact representation, or multicasting. Each compaction technique has different properties (i.e. compression ratio, decompression time and decompression energy) and is best suited for a particular class of applications. However, existing research only deals with these methods separately. Moreover, they only analyze the compaction ratio and do not evaluate the associated energy overheads. To tackle these issues, we propose a polymorphic compression architecture that interleaves these techniques in a unique platform. The proposed architecture allows each application to take advantage of a separate compression/decompression hierarchy (consisting of various types and implementations of hardware/software decoders) tailored to its needs. Simulation results, using different applications (FFT, Matrix multiplication, and WLAN), reveal that the choice of compression hierarchy has a significant impact on compression ratio (up to 52%), decompression energy (up to 4 orders of magnitude), and configuration time (from 33n to 1.5s) for the tested applications. Synthesis results reveal that introducing adaptivity incurs negligible additional overheads (1%) compared to the overall platform area.

Area and power efficient DCT architecture for image compression

The discrete cosine transform (DCT) is one of the major components in image and video compression systems. The final output of these systems is interpreted by the human visual system (HVS), which is not perfect. The limited perception of human visualization allows the algorithm to be numerically approximate rather than exact. In this paper, we propose a new matrix for discrete cosine transform. The proposed 8 × 8 transformation matrix contains only zeros and ones which requires only adders, thus avoiding the need for multiplication and shift operations. The new class of transform requires only 12 additions, which highly reduces the computational complexity and achieves a performance in image compression that is comparable to that of the existing approximated DCT. Another important aspect of the proposed transform is that it provides an efficient area and power optimization while implementing in hardware. To ensure the versatility of the proposal and to further evaluate the performance and correctness of the structure in terms of speed, area, and power consumption, the model is implemented on Xilinx Virtex 7 field programmable gate array (FPGA) device and synthesized with Cadence® RTL Compiler® using UMC 90 nm standard cell library. The analysis obtained from the implementation indicates that the proposed structure is superior to the existing approximation techniques with a 30% reduction in power and 12% reduction in area.

English

Static images of colour clouds play an important role to predict weather conditions to schedule proof and trial activities, and deploying resources at firing locations and observation posts. In this paper, a new inter-level cloud compression architecture and algorithm has been presented. Distributed architecture suitable for cloud computing has been suggested to implement inter-level compression algorithm (ILCA). Different possibilities between two successive cloud images have been combined to save the images of interest for further processing, ignoring the redundant ones. Vector quantisation technique is briefly discussed to achieve high level of compression. The algorithm presented in this paper can be easily modified to store flying, floating, and moving objects in air, water, and surface, respectively with high level of compression in various defence applications. Science Journal, Vol. 64, No. 6, November 2014, pp.536-541, DOI:http://dx.doi.org/10.14429/dsj.64.8115

Application Specific Integrated Circuit Implementation of Multiplier Free Modified Flipping Architecture for Image Compression

Application Specific Integrated Circuit Implementation of Multiplier Free Modified Flipping Architecture for Image Compression

Efficient Comparator based Sum of Absolute Differences Architecture for Digital Image Processing Applications

prolific use of images & videos in portable devices, raised the need to develop the efficient architectures for the ever increasing demand of portability with low power and high performance quality metrics. However the images and videos are the information's to be stored, but there compression while storing is the important part. This paper introduces a basic hardware component for the compression architectures. Comparator augments as general purpose core to Sum of Absolute difference (SAD) architecture used for the object recognition, generation of disparity maps of the stereo images and for estimating the motion in videos. The Subtraction part of the comparator is optimized by providing the parallel computation in processing the 2's complement operation. Transistor stacking and Logic optimization concepts are utilized to reduce the leakage power of the comparator design. 4-bit wide Comparator with smallest of two binary numbers functionality is modeled using Verilog HDL and synthesized using Synopsys Design Compiler. The design was mapped to 65nm technological library node and results were benchmarked with respect to standard ASIC design methodology. The proposed architectures have resulted in reduced leakage power about 7- 42 % for different proposed architectures and enabled the different corners for analysis.

Efficient Architecture for Image Compression for Lifting Based Discrete Wavelet Transform

in this paper Efficient architecture for discrete wavelet transform is proposed by using lifting scheme. In arithmetic, a wavelet series is a representation of a square- integrable (real-or complex-valued) function by a certain orthonormal series generated by a wavelet. Lifting based Wavelet transform is mainly comprises of three steps that is split, predict and update, this algorithm allowed high compression ratios, preserving diagnostically important data features. For low-resolution images created with the necessity to keep predefined key diagnostic information (contractile function of the heart), high compression ratios up to 2000 could be achieved. Index Terms: Discrete Wavelet transforms, square integrable function, lifting scheme.

Space-filling curves applied to compression of ultraspectral images

Space-filling curves (SFCs) have been widely used in image compression as a way to assist prediction-based schemes by providing a method to map an $$m$$ -dimensional space into a highly correlated unidimensional space. In this paper, we not only analyze the effect of different state-of-the-art curves but also propose a novel scanning procedure applied to the preprocessing stage of an ultraspectral lossy compression architecture. Specifically, we focus on Atmospheric infrared sounder images that are good compression candidates as they account for well over 25 megapixels of information per cube. In addition, we introduce a metric to estimate the efficiency of the different SFCs and present a mathematical model that, based on the Laplacian nature of the pixels, it is used to derive bounds. Finally, to verify the accuracy of this metric, we obtain rate-distortion ratios calculated by applying the corresponding curve to the compression architecture.

2-D DWT System Architecture for Image Compression

Wavelet transform has contributed significantly in multiple areas such as image processing, compression, signal analysis, and medical imaging. Discrete wavelet transform (DWT) requires very large memory requirement and is computationally intensive, especially for 2-D transform that has a quadratic computational complexity. In this paper, we propose a dedicated processor for 2-D DWT computation. The DWT system architecture is parameterizable, where its performance can be scaled by increasing or reducing the DWT engines, according to different application needs. This architecture requires significantly less computational resources and internal memory. The proposed architecture can achieve a theoretical throughput of 138 frames per second for a 2048 × 1536 video processing. The DWT system has been designed for scalability to support up to 8 parallel DWT engines.

Visual saliency guided video compression algorithm

Recently Saliency maps from input images are used to detect interesting regions in images/videos and focus on processing these salient regions. This paper introduces a novel, macroblock level visual saliency guided video compression algorithm. This is modelled as a 2 step process viz. salient region detection and frame foveation. Visual saliency is modelled as a combination of low level, as well as high level features which become important at the higher-level visual cortex. A relevance vector machine is trained over 3 dimensional feature vectors pertaining to global, local and rarity measures of conspicuity, to yield probabilistic values which form the saliency map. These saliency values are used for non-uniform bit-allocation over video frames. To achieve these goals, we also propose a novel video compression architecture, incorporating saliency, to save tremendous amount of computation. This architecture is based on thresholding of mutual information between successive frames for flagging frames requiring re-computation of saliency, and use of motion vectors for propagation of saliency values.

Robust Data Compression for Irregular Wireless Sensor Networks Using Logical Mapping

We propose RIDA, a novel robust information-driven data compression architecture for distributed wireless sensor networks. The key idea is to determine the data correlation among a group of sensors based on the data values to significantly improve compression performance rather than relying solely on spatial data correlation. A logical mapping approach assigns virtual indices to nodes based on the data content, which enables simple implementation of data transformation on resource-constrained nodes without any other information. We evaluate RIDA with both discrete cosine transform (DCT) and discrete wavelet transform (DWT) on publicly available real-world data sets. Our experiments show that 30% of energy and 80–95% of bandwidth can be saved for typical multihop data networks. Moreover, the original data can be retrieved after decompression with a low error of about 3%. In particular, for one state-of-the-art distributed data compression algorithm for sensor networks, we show that the compression ratio is doubled by using logical mapping while maintaining comparable mean square error. Furthermore, we also propose a mechanism to detect and classify missing or faulty nodes, showing accuracy and recall of 95% when half of the nodes in the network are missing or faulty.

Fast Lossless Compression of Medical Images based on Polynomial

In this paper, a fast lossless image compression method is introduced for compressing medical images, it is based on splitting the image blocks according to its nature along with using the polynomial approximation to decompose image signal followed by applying run length coding on the residue part of the image, which represents the error caused by applying polynomial approximation. Then, Huffman coding is applied as a last stage to encode the polynomial coefficients and run length coding. The test results indicate that the suggested method can lead to promising performance. General Terms Polynomial approximation within high synthetic coding architecture for lossless image compression.

Architecture and evolution of a minute plant genome

It has been argued that the evolution of plant genome size is principally unidirectional and increasing owing to the varied action of whole-genome duplications (WGDs) and mobile element proliferation1. However, extreme genome size reductions have been reported in the angiosperm family tree. Here we report the sequence of the 82-megabase genome of the carnivorous bladderwort plant Utricularia gibba. Despite its tiny size, the U. gibba genome accommodates a typical number of genes for a plant, with the main difference from other plant genomes arising from a drastic reduction in non-genic DNA. Unexpectedly, we identified at least three rounds of WGD in U. gibba since common ancestry with tomato (Solanum) and grape (Vitis). The compressed architecture of the U. gibba genome indicates that a small fraction of intergenic DNA, with few or no active retrotransposons, is sufficient to regulate and integrate all the processes required for the development and reproduction of a complex organism.

Multistage A2LVQ architecture and implementation for image compression

Abstract This paper presents the implementation of two hardware architectures, i.e., A2 Lattice Vector Quantization (LVQ) and Multistage A2LVQ (MA2LVQ), using a Field-Programmable Gate Array (FPGA). First, the renowned LVQ quantizer by Conway and Sloane is implemented followed by a low-complexity A2LVQ based on a new A2LVQ algorithm. It is revealed that the implementation requires high number of multiplier circuits. Then the implementation of a low-complexity A2LVQ is presented. This implementation uses only the first quadrant of the A2 lattice Voronoi region formed by W and T regions. This paper also presents the implementation of a multistage A2LVQ (MA2LVQ) with an architecture built from successive A2 quantizer blocks. Synthesis results show that the execution time of the low-complexity A2LVQ reaches up to 35.97 ns. The MA2LVQ is implemented using both low-complexity A2LVQ and ordinary A2 architectures. The system with the former architecture utilizes less logic and register elements by 47%.

Correction and Comment on “An Adaptive Resolution Asynchronous ADC Architecture for Data Compression in Energy Constrained Sensing Applications”

This comment points out an error in a well accepted fundamental signal-to-noise ratio (SNR) equation for asynchronous ADCs, and presents a correct SNR equation. Meanwhile, a wrong concept of calculating mean-related quantities for non-uniform sampling analysis is corrected. The result is validated by MATLAB simulation.

Low Power Compressed Context Architecture Based Processor Design

ACGR A that is focused on data path computations for a particular application domain is a balancing act akin to designing an ASIC and a FPGA simultaneously. Narrowing the application domain significantly makes the design of the CGRA very much like that of a programmable ASIC. Widening the application domain requires a more flexible data path that requires more configurable over head and has less overall efficiency compared to an FPGA. Are configurable architecture issued with compressed context architecture in ALU arrays. There by reducing power in cache (context memory). Architecture presented is replaceable to all processors including DSP processors and power can be reduced. Keyword: Coarse-grained reconfigurable architecture (CGRA), configuration cache, context architecture, low power

Delta-compressed caching for overcoming the write bandwidth limitation of hybrid main memory

Limited PCM write bandwidth is a critical obstacle to achieve good performance from hybrid DRAM/PCM memory systems. The write bandwidth is severely restricted in PCM devices, which harms application performance. Indeed, as we show, it is more important to reduce PCM write traffic than to reduce PCM read latency for application performance. To reduce the number of PCM writes, we propose a DRAM cache organization that employs compression. A new delta compression technique for modified data is used to achieve a large compression ratio. Our approach can selectively and predictively apply compression to improve its efficiency and performance. Our approach is designed to facilitate adoption in existing main memory compression frameworks. We describe an instance of how to incorporate delta compression in IBM's MXT memory compression architecture when used for DRAM cache in a hybrid main memory. For fourteen representative memory-intensive workloads, on average, our delta compression technique reduces the number of PCM writes by 54.3%, and improves IPC performance by 24.4%.

A novel ROM compression architecture for DDFS utilizing the parabolic approximation of equi-section division

In this paper, we propose the parabolic approximation of equi-section division (PAESD) utilizing the symmetry property and amplitude approximation of a sinusoidal waveform to design a direct digital frequency synthesizer (DDFS). The sinusoidal phase of a one-quarter period is divided into equi-sections. The proposed method utilizes the curvature equivalence to derive each parabolic curve function, and then the value of the error function between each parabolic curve function and the sinusoidal function is stored in an error-compensation ROM to reconstruct the real sinusoidal waveform. The upper/lower bound of the maximum error value stored in the error-compensation ROM is derived to determine the minimum required memory word length relative to the number of bits of the equi-sections. Thus, the minimum size of the total ROMs of the DDFS using the PAESD without error-compensation ROM is compressed to 544 bits; the total compression ratio, compared with the minimum size of the total ROMs of the DDFS using the basic look-up table (LUT), is approximately 843:1, achieved by consuming additional circuits [71 adaptive look-up tables (ALUTs), 3 digital signal processor (DSP) block 9-bit elements]. Consequently, the results show that the proposed ROM compression method can effectively achieve a better compression ratio than the state-of-the-art solutions without affecting the spectrum performance of an average spurious-free dynamic range (SFDR) of -85 dBc.