Compression Architecture Research Articles

Fast Implementation of Lifting based 1D/2D/3D DWT-IDWT Architecture for Image Compression

Technological growth in semiconductor industry have led to unprecedented demand for faster, area efficient and low power VLSI circuits for complex image processing applications. DWT-IDWT is one of the most popular IP that is used for image transformation. In this work, a high speed, low power DWT/IDWT architecture is designed and implemented on ASIC using 130 nm Technology. 2D DWT architecture based on lifting scheme architecture uses multipliers and adders, thus consuming power. This paper addresses power reduction in multiplier by proposing a modified algorithm for BZFAD multiplier. The proposed BZFAD multiplier is 65% faster and occupies 44% less area compared with the generic multipliers. The DWT architecture designed based on modified BZFAD multiplier achieves 35% power saving and operates at frequency of 200 MHz with latency of 1536 clock cycles for 512x512 images. The 3D-DWT architecture is designed for 8x8x8 video frame, based on fast lifting scheme approach using (9, 7) wavelet filter. Using 9/7 filter for DWT computation reduces the hardware complexity, memory accesses and achieves minimum error in reconstruction of images. The proposed architecture systematically combines hardware optimization techniques to develop a flexible DWT architecture that has high performance and is suitable for portable, high speed, low power applications. 3D-DWT architecture has been implemented on Virtex-5 FPGA with utilization of 1,152 out of 19,200 (5%) slice registers and the frequency of operation is 256 MHz. The designed DWT-IDWT can be used as IP Core.

Viterbi-Based Efficient Test Data Compression

This paper presents a Viterbi-based test compression algorithm/architecture that provides high encoding efficiency and scalability with respect to the number of test channels. The proposed scheme finds a set of compressed test vectors using the Viterbi algorithm instead of solving linear equations. By assigning a cost function to the branch metric of the Viterbi algorithm, an optimal compressed vector is selected among the possible solution set. This feature enables high flexibility to combine various test requirements such as low-power compression and/or improving capability to repeat test patterns. The proposed on-chip decompressor follows the structure of Viterbi encoders which require only one input channel. Experimental results on test volume show improvement on all ISCAS89 benchmark circuits (19.32% reduction on the average) compared to previous test data compression architectures. The proposed scheme also yields efficient power-dissipation/volume tradeoff.

Model-Based Multichannel Compressive Sampling with Ultra-Low Sampling Rate

The emerging compressive sampling (CS) theory makes processing ultra-wide-band (UWB) signal at a low sampling rate possible if the underlying signal has a sparse representation in a certain basis. The feasibility of model based compressive sampling for ultra-wide-band (UWB) signal is investigated. In this paper, a multichannel compressive sampling architecture is developed to capture UWB signal at a rate much lower than Nyquist rate. The proposed framework considers sub-Nyquist sampling stream of delayed and weighted versions of a known signal with finite support in time domain. A basis function is constructed to realize sparse signal representation. To reduce the hardware cost, a segmented architecture is suggested. In addition, a joint signal recovery algorithm is presented. Experimental results indicate that, with this system, a UWB signal sampled at about 4% of Nyquist rate still can be recovered with overwhelming probability.

Space–time compressive imaging

Compressive imaging systems typically exploit the spatial correlation of the scene to facilitate a lower dimensional measurement relative to a conventional imaging system. In natural time-varying scenes there is a high degree of temporal correlation that may also be exploited to further reduce the number of measurements. In this work we analyze space-time compressive imaging using Karhunen-Loève (KL) projections for the read-noise-limited measurement case. Based on a comprehensive simulation study, we show that a KL-based space-time compressive imager offers higher compression relative to space-only compressive imaging. For a relative noise strength of 10% and reconstruction error of 10%, we find that space-time compressive imaging with 8×8×16 spatiotemporal blocks yields about 292× compression compared to a conventional imager, while space-only compressive imaging provides only 32× compression. Additionally, under high read-noise conditions, a space-time compressive imaging system yields lower reconstruction error than a conventional imaging system due to the multiplexing advantage. We also discuss three electro-optic space-time compressive imaging architecture classes, including charge-domain processing by a smart focal plane array (FPA). Space-time compressive imaging using a smart FPA provides an alternative method to capture the nonredundant portions of time-varying scenes.

Low-memory video compression architecture using strip-based processing for implementation in wireless multimedia sensor networks

This paper presents a very low-memory video compression architecture for implementation in a wireless multimedia sensor network. The approach employs a strip-based processing technique where a group of image sequences is partitioned into strips, and each strip is encoded separately. A new one-dimensional, memory-addressing method is proposed to store the wavelet coefficients at predetermined locations in the strip buffer for ease of coding. To further reduce the memory requirements, the video-coding scheme uses a modified set-partitioning in hierarchical trees algorithm to give a high compression performance. The proposed work is implemented using a soft-core microprocessor-based approach. Simulation tests conducted have verified that even though the proposed video compression architecture using strip-based processing requires a much less complex hardware implementation and its efficient memory organisation uses a lesser amount of embedded memory for processing and buffering, it can still achieve a very good compression performance.

Design and Implementation of a Lossless Serial High-Speed Data Compression System

The paper presents a novel VLSI architecture for high-speed data compressor designs which implement the X-Match algorithm. This design involves important trade off that affects the compression performance, latency, and throughput. The most promising approach is implemented into FPGA hardware. This device typical compression ratio that halves the original uncompressed data. This device is specifically targeted to enhance the performance of Gbits/s data networks and storage applications where it can double the performance of the original systems. To get high compression rate or to get high data rate of communication not restriction to follow the parallel architecture of data compression. By using existing method the main draw backs are 1. Variation in compression 2. Throughput, 3.Latency, 4.High space, 5. High power. So by using this proposed method we can reduce the variation in the compression, latency and increase through put. And this novel VLSI architecture has a power consumption of 81mwatts power

Power-aware compression scheme for multiple scan-chain

As test data continues to grow quickly, test cost also increases. For the sake of decreasing the test cost, this article presents a new data dependency compression scheme for large circuit which is based on multiple scan chains. We propose new compression architecture with fixed length for running tests. In results, when the complexity of a VLSI circuit is growing, the number of input pins for testing is very low. Since test data in power aware is not changed frequently, we use a selector to filter the unnecessary status and buffers to hold the back data. We also propose a new algorithm to assign multiple scan chains and an improved linear dependency compute method to find the hidden dependency between scan chains. Experimental results show that the proposed method can reduce both test data volume and shift-in power.

3D-TV Content Storage and Transmission

There exist a variety of ways to represent 3D content, including stereo and multiview video, as well as frame-compatible and depth-based video formats. There are also a number of compression architectures and techniques that have been introduced in recent years. This paper provides an overview of relevant 3D representation and compression formats. It also analyzes some of the merits and drawbacks of these formats considering the application requirements and constraints imposed by different storage and transmission systems.

An Adaptive Resolution Asynchronous ADC Architecture for Data Compression in Energy Constrained Sensing Applications

An adaptive resolution (AR) asynchronous analog-to-digital converter (ADC) architecture is presented. Data compression is achieved by the inherent signal dependent sampling rate of the asynchronous architecture. An AR algorithm automatically varies the ADC quantizer resolution based on the rate of change of the input. This overcomes the trade-off between dynamic range and input bandwidth typically seen in asynchronous ADCs. A prototype ADC fabricated in a 0.18 μm CMOS technology, and utilizing the subthreshold region of operation, achieves an equivalent maximum sampling rate of 50 kS/s, an SNDR of 43.2 dB, and consumes 25 μW from a 0.7 V supply. The ADC is also shown to provide data compression for accelerometer applications as a proof of concept demonstration.

A CMOS Image Sensor With On-Chip Image Compression Based on Predictive Boundary Adaptation and Memoryless QTD Algorithm

This paper presents the architecture, algorithm, and VLSI hardware of image acquisition, storage, and compression on a single-chip CMOS image sensor. The image array is based on time domain digital pixel sensor technology equipped with nondestructive storage capability using 8-bit Static-RAM device embedded at the pixel level. The pixel-level memory is used to store the uncompressed illumination data during the integration mode as well as the compressed illumination data obtained after the compression stage. An adaptive quantization scheme based on fast boundary adaptation rule (FBAR) and differential pulse code modulation (DPCM) procedure followed by an online, least storage quadrant tree decomposition (QTD) processing is proposed enabling a robust and compact image compression processor. A prototype chip including 64×64 pixels, read-out and control circuitry as well as an on-chip compression processor was implemented in 0.35 μm CMOS technology with a silicon area of 3.2×3.0 mm2 and an overall power of 17 mW. Simulation and measurements results show compression figures corresponding to 0.6-1 bit-per-pixel (BPP), while maintaining reasonable peak signal-to-noise ratio levels.

Compressing Cache State for Postsilicon Processor Debug

During postsilicon processor debugging, we need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, the bulk of which is composed of cache, the problem is essentially that of transferring cache contents off-chip, to a logic analyser. In order to reduce the transfer time and save expensive logic analyser memory, we propose to compress the cache contents on their way out. We present a hardware compression engine for cache data using a Cache-Aware Compression strategy that exploits knowledge of the cache fields and their behavior to achieve an effective compression. Experimental results indicate that the technique results in 7-31 percent better compression than one that treats the data as just one long bit stream. We also describe and evaluate a parallel compression architecture that uses multiple compression engines, resulting in a 54 percent reduction in transfer time.

Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment

As the test data continues to grow quickly, test cost also increased. For the sake of decreasing the test cost, this study presents a new compression for large circuit, which is based on multiple scan-chains and unknown structure. The proposed method is targeted at intellectual property cores and system-on-a-chip. The authors consider the shift-in power and compression ratio in low-cost automatic test equipment (ATE) environment. A new compression architecture with fixed length for running ones is proposed. For the proposed method, the ATE has no repeated function and synchronisation signal. In the results, when the complexity of very large-scale integrated circuit is growing up, the number of input pins for testing is very low. The average compression ratio of our method is 63% for MinTest and TetraMAX on ISCAS'89 benchmarks. The average of peak/weight transition count shift-in turns to 3x/6.6x for MinTest and 2.3x/5.6x for TetraMAX, after comparing selective scan slice and the proposed method. The average of hardware overhead is 6% for MinTest and 6.5% for TetraMAX.

Improved IPsec performance utilizing transport‐layer‐aware compression architecture

AbstractWith the rapid growth of applications in Internet communication, the security for transmitting information on public network has become a fundamental issue. The Internet Protocol Security (IPsec) standard is developed by Internet Engineering Task Force (IETF) to provide the security services at the IP layer. IPSec solutions invariably result in a large‐packet size and a long processing time. Accordingly, this paper proposes new compression architecture, designated as Efficient Secure Pipe (ES_PIPE), to improve both the security and the performance of IPv6 networks. In contrast to traditional IPsec compression schemes, ES_PIPE provides a transport‐layer‐aware compression capability for different types of packets (e.g., TCP or UDP/RTP packets). The experimental results show that the proposed scheme reduces 20–30% transmission time compared to IPsec. Furthermore, ES_PIPE scheme yields about 20% improvement in the efficiency of the encryption and decryption processes. Copyright © 2010 John Wiley & Sons, Ltd.

Trigonometric Transforms for High-Speed Optical Networks: All-Optical Architectures and Optical OFDM

In this paper, it is shown that the use of real trigonometric transforms can advantageously replace the Fourier transform in optical communication systems, for both all-optical and electronic signal processing. All-optical discrete Hartley transform (DHT) and discrete Cosine transform (DCT) architectures for high-speed optical signal processing, filtering and data compression are given and compared to fiber Fourier processing. A trigonometric transform-based orthogonal frequency division multiplexing (OFDM) transmission system is also presented. The modulation/demodulation is performed by using the fast Hartley transform (FHT) algorithm. The simplified scheme and the real processing make it suitable for direct detection optical systems.

Multigig lossless data compression device

This paper presents a novel lossless data compression device that extends enterprise network to branch offices by integrating multiple communication technologies. The presented device incorporates Gigabit Ethernet, STM1/STM4/STM16 interfaces for WAN connectivity, fiber channel interfaces for storage area network and 10G Ethernet interface for enterprise network connectivity. The device implements a novel architecture that implements the LZ77 lossless data compression algorithm in hardware. The high throughput data compression architecture enables the interfacing of the diverse high-speed communication technologies besides preserving the channel bandwidth for accommodating multiple applications. The device finds consumer applications to optimize WAN bandwidth, healthcare, media&broadcasting and storage area networks (SAN).

The neural architecture of discourse compression

Re-telling a story is thought to produce a progressive refinement in the mental representation of the discourse. A neuroanatomical substrate for this compression effect, however, has yet to be identified. We used a discourse re-listening task and functional magnetic resonance imaging (fMRI) to identify brain regions responsive to repeated discourse in twenty healthy volunteers. We found a striking difference in the pattern of activation associated with the first and subsequent presentations of the same story relative to rest. The first presentation was associated with a highly significant increase in blood oxygen level dependent (BOLD) signal in a bilateral perisylvian distribution, including auditory cortex. Listening to the same story on subsequent occasions revealed a wider network with activation extending into frontal, parietal, and subcortical structures. When the first and final presentations of the same story were directly compared, significant increments in activation were found in the middle frontal gyrus bilaterally, and the right inferior parietal lobule, suggesting that the spread of activation with re-listening reflected an active neural process over and above that required for comprehension of the text. Within the right inferior parietal region the change in BOLD signal was highly correlated with a behavioural index of discourse compression based in re-telling, providing converging evidence for the role of the right inferior parietal region in the representation of discourse. Our findings demonstrate, for the first time, the existence of a neural network underlying discourse compression, showing that parts of this network are common to re-telling and re-listening effects.

Numerical analysis of hardware architecture for header compression and packet aggregation on wireless networks

This paper proposes a numerical analysis model to predict the processing delay of a hardware architecture for robust header compression and packet aggregation on wireless mesh networks. The analysis model is composed of a series of queue systems such as G/M/1, M [K]/M/1, M/M/1, and M/M/� that are one-to-one mapped into the constructed hardware components to characterize the concurrent operations and interactional relationship between encoding and decoding paths. Based on the co-simulation method which integrates NS-2 and SystemC, we show the analysis model properly approximates the processing delay of the hardware architecture. Additionally, the variation of processing delay occurring when a part of hardware components are differently configured is suitably characterized by the proposed model, and the overall mesh network behaviors is predicted by applying the numerical results into NS-2 simulations.

A New Architecture of a Two-Stage Lossless Data Compression and Decompression Algorithm

In this paper, we propose a new architecture for the two-level lossless data compression and decompression algorithm proposed in that combines the PDLZW algorithm and an approximated adaptive Huffman algorithm with dynamic-block exchange (AHDB). In the new architecture, we replace the CAM dictionary set used in the PDLZW algorithm with a CAM-tag-based dictionary set to reduce hardware cost and the CAM-based ordered list used in the AHDB algorithm with a memory inter-reference (MIR) stage realized by using two SRAMs. The resulting architecture is then implemented based on cell-based libraries with both 0.35-mum 2P4M and 0.18-mum 1P6M process technologies, respectively. With the same process technology, the prototyped chip demonstrates the new architecture not only has better performance, at least 33% improvement, but also occupies less area, only about 44%, and consumes less power, about 50%, in comparison with the architecture proposed in . In addition, the maximum data rate can achieve 2 Gbps when realizing in 0.35 mum 2P4M process technology and 4 Gbps when realizing in 0.18-mum 1P6M process technology.

Focal-Plane Change Triggered Video Compression for Low-Power Vision Sensor Systems

Video sensors with embedded compression offer significant energy savings in transmission but incur energy losses in the complexity of the encoder. Energy efficient video compression architectures for CMOS image sensors with focal-plane change detection are presented and analyzed. The compression architectures use pixel-level computational circuits to minimize energy usage by selectively processing only pixels which generate significant temporal intensity changes. Using the temporal intensity change detection to gate the operation of a differential DCT based encoder achieves nearly identical image quality to traditional systems (4dB decrease in PSNR) while reducing the amount of data that is processed by 67% and reducing overall power consumption reduction of 51%. These typical energy savings, resulting from the sparsity of motion activity in the visual scene, demonstrate the utility of focal-plane change triggered compression to surveillance vision systems.

Real-time compression architecture for efficient coding in autostereoscopic displays

Integral imaging is a promising technique for delivering high-quality three-dimensional content. However, the large amounts of data produced during acquisition prohibits direct transmission of Integral Image data. A number of highly efficient compression architectures are proposed today that outperform standard two-dimensional encoding schemes. However, critical issues regarding real-time compression for quality demanding applications are a primary concern to currently existing Integral Image encoders. In this work we propose a real-time FPGA-based encoder for Integral Image and integral video content transmission. The proposed encoder is based on a highly efficient compression algorithm used in Integral Imaging applications. Real-time performance is achieved by realizing a pipelined architecture, taking into account the specific structure of an Integral Image. The required memory access operations are minimized by adopting a systolic concept of data flow through the core processing elements, further increasing the performance boost. The encoder targets, real-time, broadcast-type high-resolution Integral Image and video sequences and performs three orders of magnitude faster than the analogous software approach.