Low Power Compressed Context Architecture Based Processor Design

Abstract

ACGR A that is focused on data path computations for a particular application domain is a balancing act akin to designing an ASIC and a FPGA simultaneously. Narrowing the application domain significantly makes the design of the CGRA very much like that of a programmable ASIC. Widening the application domain requires a more flexible data path that requires more configurable over head and has less overall efficiency compared to an FPGA. Are configurable architecture issued with compressed context architecture in ALU arrays. There by reducing power in cache (context memory). Architecture presented is replaceable to all processors including DSP processors and power can be reduced. Keyword: Coarse-grained reconfigurable architecture (CGRA), configuration cache, context architecture, low power