Compliant Interconnects Research Articles

Design and Fabrication of FlexConnects: A Cost-Effective Implementation of Compliant Chip-to-Substrate Interconnects

Compliant free-standing structures can be used as chip-to-substrate interconnects. Such ldquocompliant interconnectsrdquo are a potential solution to the requirements that will be imposed on chip-to-substrate interconnects over the next decade. However, cost of implementation and electrical performance limit compliant interconnects. This paper presents two concepts to address this. First, an innovative, cost-effective fabrication process to realize compliant interconnects is proposed. Sequential lithography and electroplating processes with up to two masking steps are utilized. Such an approach potentially reduces the cost of fabricating compliant interconnects. Second, an innovative approach to designing compliant interconnects is proposed to improve electrical performance without compromising on mechanical reliability. The new approach uses parallel/multiple electrical paths as part of the compliant interconnect design. These concepts are integrated to realize a new compliant interconnect technology called FlexConnects. Utilizing the proposed fabrication process parallel-path FlexConnects are realized at a 100-mum pitch. Numerical simulations are used to demonstrate that the electrical performance of parallel-path FlexConnects (self inductance of ~ 37 pH) is enhanced without compromising on mechanical performance, validating the use of parallel/multiple electrical paths in the interconnect design.

Thermomechanical Reliability of Nickel Pillar Interconnections Replacing Flip-Chip Solder Without Underfill

Interconnect technologies between ICs and packages or boards have a significant impact on the IC performance and packaging density. Today, the interconnections are typically accomplished with either wire bonding or flip-chip solders. While both of these technologies are incremental, they also run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect might not satisfy the thermomechanical reliability requirements at very fine-pitches. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. This paper reports fine-pitch interconnection technologies using nano-structured nickel as primary interconnection material. The nano-grained nickels are produced by electroplating process. The primary nano-structured interconnects are assembled with different bonding methods to provide organic compatible low-temperature fabrication. Au-Sn and Sn-Cu are used for solder-based assembly of nano-nickel interconnections. Low modulus anisotropic conductive films (ACFs) are also used as an alternate bonding route of the solders. No underfilling is used in all the interconnect structures evaluated in this paper. Assembly are accomplished on different coefficient of thermal expansion (CTE) substrates including FR-4 with 18 ppm/degC, advanced organic substrates with 10 ppm/degC, novel low CTE (3 ppm/degC) substrates based on carbon-silicon carbide (C-SiC). The thermomechanical reliability of all the nano-interconnects assembled on different CTE substrates with different bonding approaches is evaluated by thermal shock testing and finite-element analysis. Nano-nickel interconnects bonded with the ACF showed the highest reliability withstanding 1500 cycles. In all cases, no apparent failure was observed in the primary nano-nickel metal interconnects. This technology is expected to be easily downscaled to submicrometer and nano-scale unlike the current solder technologies leading to true nano-interconnections.

Low-K Dielectric Compatible Wafer-Level Compliant Chip-to-Substrate Interconnects

Performance, power, size, and cost requirements in the microelectronics industry are pushing for smaller feature size, innovative on-chip dielectric materials, higher number of interconnects at a reduced pitch, etc., without compromising the microelectronics reliability. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill material. These compliant interconnects are beneficial for integrated circuits (ICs) with low-K dielectric material. They are also potentially cost effective as they can be fabricated using conventional wafer fabrication infrastructure. In this paper we discuss the assembly and experimental reliability assessment, through thermal cycling, of G-Helix interconnects assembled on an organic substrate. Results from mechanical characterization experiments are also presented. It is shown that the proposed interconnects are not likely to delaminate or crack the low-K dielectric material. Also, a unique integrative approach is discussed, with interconnects having varying compliance for optimum electrical and mechanical performance.

Metal–Polymer Composite Interconnections for Ultra Fine-Pitch Wafer Level Packaging

The decrease in feature sizes of microelectronic devices has underlined the need for higher number of input-outputs (I/Os) in order to increase its functionality. This has spurred a great interest in developing electronic packages with fine and ultra fine pitches (20-100 mum). Most of the compliant interconnects that are currently being developed have inductance and resistance higher than desirable. This paper presents a novel low-temperature fabrication process that combines polymer structures with electroless copper plating to create low stress composite structures for extremely fine-pitch wafer level packages. Analytical models for these structures justify the stress reduction at the interfaces and superior reliability as integrated circuit (IC)-package interconnects. Low coefficient of thermal expansion (CTE) polyimide structures with ultra-low stress, high toughness, and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80deg. The etching process also leads to roughened sidewalls for selective electroless copper plating on the sidewalls of polymer structures. This work also describes a selective electroless plating synthesis route to develop thin IC-package bonding interfaces with lead-free solder. Lead-free alloy films were deposited from aqueous plating solutions consisting of suitable metal salts and reducing agents at 45degC. The lead-free solder composition was controlled by altering the plating bath formulation. Solder film formed from the above approach was demonstrated to bond the metal-coated polymer interconnects with the copper pads on the substrate using a standard reflow process. Metal-coated polymer structures in conjunction with the thin solder bonding films can provide low-cost high-performance solutions for wafer-level packaging.

Assembly of Copper Column Interconnect Flip Chip

This paper addresses a new flip chip interconnection technology, flexible flip chip connection (F2C2) technology, for attaching silicon chips to a chip carrier using flexible copper wires. F2C2 is a novel approach to create area array flip chip interconnections using a matrix block of wires encapsulated with a heat-resistant, dissolvable substance. A slice from the wire matrix ingot is first attached to the chip using solder. The other end of the slice is then matched and soldered to the footprint of a substrate. Finally, the encapsulating, dissolvable substance is removed from the body of the slice, leaving the chip attached to the carrier by the inter- disposed, flexible copper wires. The compliant copper wire interconnections can accommodate the coefficient of thermal expansion (CTE) mismatch problem between die and substrate, thus eliminating the need for underfill.

A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

Erratum: “Microfabrication of ultrahigh density wafer-level thin film compliant interconnects for through-silicon-via based chip stacks” [J. Vac. Sci. Technol. B 24, 1780 (2006)

First Page

Microfabrication of ultrahigh density wafer-level thin film compliant interconnects for through-silicon-via based chip stacks

The current trend in wafer-level three-dimensional integration is by copper-filled through-silicon vias (TSVs) which considerably minimize signal transmission time due to the short wiring length required to integrate vertically stacked chips. However, the present wire bonding technology widely used in peripheral integration of stacked chips cannot integrate TSV based chip stacks. This article describes the fabrication methodology of a thin film compliant interconnect referred to as Smart Three Axis Compliant (STAC) interconnects which can be directly integrated onto TSV based chip stacks. These batch processed compliant interconnects are successfully fabricated utilizing microelectromechanical systems technology at the wafer level by magnetron sputtering oppositely stressed layers of TiW films. Once patterned and released, STAC interconnects easily achieve input/output counts of 104∕cm2 or greater, making it suitable to be directly integrated onto through-silicon-via based chip stacks.

Sea-of-Leads MEMS I/O Interconnects for Low-k IC Packaging

Technology feasibility of MEMS-type chip I/O interconnects (namely Sea-of-Leads or SoL) is demonstrated. Acting like a spring, a MEMS lead can provide high mechanical compliance to compensate for mismatch of coefficient of thermal expansion (CTE) between a Si chip and a composite substrate. The compliant interconnects can provide low-stress connection between a chip and a PWB substrate, and, therefore, are promising to enable wafer-level packaging of IC chips with mechanically weak low-k interlayer dielectrics (ILD). The compliant interconnection also eliminates the need for an expensive underfilling process, which is one of the key challenges for scaling of conventional controlled collapse chip connection (C4) solder bumps in organic flip-chip packages. For the first time, SoL MEMS interconnects were investigated through the whole procedure of process integration, assembly, as well as reliability assessment. Without underfill, the SoL MEMS interconnects survived more than 500 thermal cycles indicating a promising improvement over a regular C4 solder joint. Failure analysis suggests that the MEMS leads do not fracture while failure occurs close to solder-Cu pad interface due to a nonreliable joining. Full reliability potential of the SoL MEMS interconnects may be demonstrated upon optimization of PWB metallurgy, soldermask design and lead compliance.

Sea of leads compliant I/O interconnect process integration for the ultimate enabling of chips with low-k interlayer dielectrics

Sea of leads (SoL) process integration for the series of steps required to transform a fully intact die at the wafer level to a die that is assembled onto a board is described. The primary goal is to address the issues involved in reconciling the fabrication and assembly requirements of compliant leads, such as SoL, with those of standard semiconductor processes and chip assembly techniques. The effort is motivated in-part by the potential failure of the low-k interlayer dielectric in microprocessors as a result of high mechanical stresses due to the coefficient of thermal expansion (CTE) mismatch between the chip and the board. SoL, and other compliant interconnections, mitigate this problem by mechanically decoupling the chip and the board. While compliant leads offer advantages over C4 technology, there is much to consider during the series of steps needed to transform the fully intact dice at the wafer level to dice that are assembled onto the board. The use of an encapsulation film over the leads during wafer sawing is shown to be necessary for slippery leads and other free-standing compliant leads. The use of a suitable flux when the leads are finished with a nickel-oxide nonwettable layer is essential for a successful wafer-level solder reflow. Successful die assembly using thermocompression bonding is demonstrated using two different SoL dice with correspondingly different substrates. The resistance of a chain of 30 cascaded leads is 2.7 /spl Omega/.

Mechanical, thermal, and electrical analysis of a compliant interconnect

Ball grid array (BGA) package styles use solder balls as electrical interconnects between packages and application boards. Solder balls are rigid and tend to fracture under thermal fatigue and/or shock loading. Metalized polymer spheres (MPS) offer a more compliant interconnect, compared to solder balls, thereby increasing the thermal cycling fatigue life. A reduction in thermal and electrical performance may be expected for MPS interconnects as a result of its higher thermal and electrical resistances. A 5% and an 8% increase in MPS thermal resistance was measured for a carrier array ball grid array (CABGA) package and a plastic ball grid array (PBGA) package, respectively, compared to eutectic solder balls. However, this small reduction was offset by large gains in the solder joint life. A 1.6 times increase in the mean thermal fatigue life was measured for a CABGA using MPS interconnects compared to eutectic solder balls. A first-order model showed that eutectic solder balls provide greater process margins, compared to MPS interconnects, due to the ball collapse during reflow.

Development of G-Helix Structure as Off-Chip Interconnect

Microsystem packages continue to demand lower cost, higher reliability, better performance and smaller size. Compliant wafer-level interconnects show great potential for next-generation packaging. G-Helix, an electroplated compliant wafer-level chip-to-substrate interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The fabrication of the G-Helix interconnect is similar to conventional IC fabrication process and is based on electroplating and photolithography. G-Helix interconnect has good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. In this paper, we report the wafer-level fabrication of an area-arrayed G-Helix interconnects. The geometry effect on the mechanical compliance and electrical parasitics of G-Helix interconnects have been studied. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is also found that structures with excellent mechanical compliance may not have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), an optimization has been done. Furthermore, reliability of the optimized G-helix interconnects in a silicon-on-organic substrate assembly has been assessed, which includes the package weight and thermo-mechanical analysis. The pitch size effect on the electrical and mechanical performance of G-Helix interconnects has also been studied.

Next Generation of 100-<tex>$murm m$</tex>-Pitch Wafer-Level Packaging and Assembly for Systems-on-Package

According to the latest ITRS roadmap, the pitch of area array packages is expected to decrease to 100 /spl mu/m by 2009. Simultaneously, the electrical performance of these interconnections needs to be improved to support data rates in excess of 10 Gbps, while guaranteeing thermomechanical reliability and lowering the cost. These requirements are challenging, thus, needing innovative interconnection designs and technologies. This paper describes the development of three interconnection schemes for wafer-level packages (WLPs) at 100-/spl mu/m pitch, involving rigid, compliant, and semicompliant interconnection technologies, extending the state of the art in each. Extensive electrical and mechanical modeling was carried out to optimize the geometry of the interconnections with respect to electrical performance and thermomechanical reliability. It was found that the requirements of electrical performance often conflict with those of thermomechanical reliability and the final optimum design is a tradeoff between the two. For the three interconnection schemes proposed, it was found that the electrical requirements can be met fairly well but acceptable mechanical reliability may require organic boards with a coefficient of thermal expansion of 10 ppm/K or lower.

β-Helix: A lithography-based compliant off-chip interconnect

Microsystems packages continue to demand lower cost, higher reliability, better performance and smaller size. Compliant wafer-level interconnects show great potential for next-generation packaging. The proposed /spl beta/-Helix interconnect, an electroplated compliant wafer-level off-chip interconnect, can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The fabrication of the /spl beta/-Helix interconnect is similar to conventional integrated circuit (IC) fabrication processes and is based on electroplating and photolithography. /spl beta/-Helix interconnect has good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. In this paper, we report the wafer-level fabrication of area-arrayed /spl beta/-Helix interconnects. The geometry effect on the mechanical compliance and the electrical parasitics of /spl beta/-Helix interconnect has been studied. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is also found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), an optimization has been done, and the optimal compliant /spl beta/-Helix interconnect will have a total standoff height of 110 /spl mu/m, radius of 37 /spl mu/m and cross section area of 525 /spl mu/m/sup 2/. It is also found that the structure self-weight effect during the fabrication and the die and heat sink weights during the assembly have negligible effect on the /spl beta/-Helix interconnect, especially when the interconnect density is high.

Study of coupled thermal electric behavior of compliant micro-spring interconnects for next generation probing applications

Advances in integrated circuit fabrication have given rise to a need for an innovative, inexpensive, yet reliable probing technology with ultra-fine pitch capability. Flexible micro-spring structures that can exceed the probing needs of the next-generation microelectronic devices have been developed. Highly compliant cantilevered springs have been fabricated at pitches as small as 6/spl mu/m. These micro-springs are designed to accommodate topological variation in probing surfaces while flexing within the elastic regime. Coupled thermal-electric numerical models have been developed to understand the thermal contours and current density developed across these springs. Based on the models and experiments, it is seen that the electrical resistance of the probe spring under study will be less than 1 /spl Omega/. Also, it is seen that the maximum temperature due to Joule heating is localized near the tip of the probe and can be about 93/spl deg/C above the ambient temperature, when temperature dependent bulk material properties are used. Optimization of the spring geometry to reduce this maximum temperature is outlined. In addition, the role of scale effects on the thermal conductivity of the spring material is studied. Based on the work, it can be said that it is possible to design micro-contact springs for probing applications such that the electrical resistance and the temperature increase during probing will be within acceptable limits.

Design optimization of one-turn helix: A novel compliant off-chip interconnect

As the rapid advances in integrated circuit (IC) design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great potential for next-generation packaging. One-turn helix (OTH) interconnect, a compliant chip-to-next level substrate or off-chip interconnect, is proposed in this work, and this interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The interconnect has high mechanical compliance in the three orthogonal directions, and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of the helix interconnect is similar to the standard IC fabrication, and the wafer-level packaging makes it cost effective. In this paper, we report the fabrication of an area array of helix interconnects on a silicon wafer. Also, we have studied the effect of interconnect geometry parameters on its mechanical compliance and electrical parasitics. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of OTH interconnect. An optimization technique using response surface methodology has been applied to select the optimal structure parameters. The optimal compliant OTH interconnect will have a total standoff height of about 100 /spl mu/m, a radius of about 35 /spl mu/m and a cross section area of about 430 /spl mu/m/sup 2/.

Isotonic muscle and sarcomere shortening in rabbit right ventricular preparations.

Cardiac muscle fibers are suspended within and attached to an elaborate connective tissue matrix that includes numerous compliant interconnections. Myocardial muscle fibers are not branched, but connect at small angles to each other to form a branched array. Therefore, fiber shortening occurs as a vector within a connective tissue framework and individual fiber work may exceed external muscle work. To evaluate the latter we measured isotonic muscle shortening simultaneous with sarcomere shortening. The hearts were obtained from rabbits (n = 4) anesthetized with intravenous pentobarbital sodium. We isolated right ventricular trabeculae or free wall papillary muscles in Krebs-Ringer's solution (2.5 mM Ca2+, 28 degrees C). Cross-sectional area was 0.038 +/- 0.003 mm2 (+/- SE throughout) and resting sarcomere length was 2.33 +/- 0.12 microns. Sarcomere length was measured with laser diffraction (He-Ne, lambda = 632.8 nm) during force clamps in single- and paired-stimulation twitches. Relative sarcomere shortening (delta SL) was isotonic sarcomere shortening divided by sarcomere length at the onset of isotonic shortening. Relative muscle shortening (delta ML) was isotonic muscle shortening divided by muscle length at zero load; the latter was estimated from the stress-strain relation of elastic recoil at the onset of load clamps. Average delta SL/delta ML at peak shortening was 3.38 +/- 0.16 and was independent of stimulus pattern, isotonic load, amount of shortening, time during a twitch or laser beam position along a muscle. Therefore, the ratio greater than 1 was neither a function of activation nor heterogeneous sarcomere length change.(ABSTRACT TRUNCATED AT 250 WORDS)