Metal–Polymer Composite Interconnections for Ultra Fine-Pitch Wafer Level Packaging

Abstract

The decrease in feature sizes of microelectronic devices has underlined the need for higher number of input-outputs (I/Os) in order to increase its functionality. This has spurred a great interest in developing electronic packages with fine and ultra fine pitches (20-100 mum). Most of the compliant interconnects that are currently being developed have inductance and resistance higher than desirable. This paper presents a novel low-temperature fabrication process that combines polymer structures with electroless copper plating to create low stress composite structures for extremely fine-pitch wafer level packages. Analytical models for these structures justify the stress reduction at the interfaces and superior reliability as integrated circuit (IC)-package interconnects. Low coefficient of thermal expansion (CTE) polyimide structures with ultra-low stress, high toughness, and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80deg. The etching process also leads to roughened sidewalls for selective electroless copper plating on the sidewalls of polymer structures. This work also describes a selective electroless plating synthesis route to develop thin IC-package bonding interfaces with lead-free solder. Lead-free alloy films were deposited from aqueous plating solutions consisting of suitable metal salts and reducing agents at 45degC. The lead-free solder composition was controlled by altering the plating bath formulation. Solder film formed from the above approach was demonstrated to bond the metal-coated polymer interconnects with the copper pads on the substrate using a standard reflow process. Metal-coated polymer structures in conjunction with the thin solder bonding films can provide low-cost high-performance solutions for wafer-level packaging.