Thermal and Reliability Demonstration of a Large Die on a Low CTE Chip Scale Package

Abstract

In organic packages, large die and large laminate body sizes are susceptible to CTE (coefficient of thermal expansion) mismatch driven warpage, stresses and strains, which can result in C4 white bumps, micro Ball Grid Array (BGA) interconnection issues, and package thermal reliability concerns. Low CTE carriers minimize these concerns and allow increased chip join yields and improved package reliability. Modeling and characterization of warpage, chip and micro BGA integrity and electrical characterization of a low CTE, Chip Scale Package (CSP) were described in an earlier paper. In this paper we report the progress on the next phase - thermal and chip package interaction (CPI) evaluation of a single chip CSP designed for use with Multi-Chip Modules (MCM). Assembly, characterization, thermal performance and reliability stress results of these low CTE CSP Single Chip Modules (SCMs) are described. Measured warpage values are compared with thermo-mechanical modeling results. Demonstration of a dual CSP design and assembly with large dies is also presented. The successful demonstration of the material set, bond and assembly processes, and reliability of a large die, high I/O CSP, followed by the demonstration of a dual CSP on a multi component carrier, are fore-runners to the development of multi-CSP MCMs.