Complex Digital Circuits Research Articles

Cooperative and Progressive Design Experience for Embedded Systems

This paper describes a cooperative experiential learning activity to develop embedded systems design skills. Student teams design, build, and troubleshoot a microcontroller-based project composed of common embedded systems peripherals, including input/output and electromechanical devices, industry standard communication networks, and complex digital integrated circuits. The design experience is progressive, requiring each successive subsystem to be incorporated without disturbing previously completed subsystems. Furthermore, the design experience is based on a problem-based learning approach that motivates student learning and develops skills required by the student in a future professional capacity. These skills include designing to specification, use of third-party intellectual property, teamwork, communication, and lifelong learning skills. The design experience was offered to a cohort in conjunction with lectures using active learning techniques. Course evaluations were obtained from students and external reviewers, and the results show that the course was well received and achieved its educational objectives.

Digital LMS adaptation of analog filters without gradient information

The least mean square (LMS) algorithm has practical problems in the analog domain mainly due to DC offset effects. If digital LMS adaptation is used, a digitizer (analog-to-digital converter or comparator) is required for each gradient signal as well as the filter output. Furthermore, in some cases the state signals are not available anywhere in the analog signal path necessitating additional analog filters. Here, techniques for digitally estimating the gradient signals required for the LMS adaptation of analog filters are described. The techniques are free from DC offset effects and do not require access to the filter's internal state signals. Digitizers are required only on the input and error signal. The convergence rate and misadjustment are identical to traditional LMS adaptation, but an additional matrix multiplication is required for each iteration. Hence, analog circuit complexity is reduced but digital circuit complexity is increased with no change in overall performance making it an attractive option for mixed-signal integrated systems in digital CMOS. Signed and subsampled variations of the adaptive algorithm can provide a further reduction in analog and digital circuit complexity, but with a slower convergence rate. Theoretical analyses, behavioral simulations, and experimental results from an integrated filter are all presented.

Digital processing with a three-state molecular switch.

Certain molecular switches respond to input stimulations producing detectable outputs. The interplay of these signals can be exploited to reproduce basic logic operations at the molecular level. The transition from simple logic gates to complex digital circuits requires the design of chemical systems able to process multiple inputs and outputs. We have identified a three-state molecular switch that responds to one chemical and two optical inputs producing two optical outputs. We have encoded binary digits in its inputs and outputs applying positive logic conventions and demonstrated that this chemical system converts three-digit input strings into two-digit output strings. The logic function executed by the three-state molecular switch is equivalent to that of a combinational logic circuit integrating two AND, two NOT, and one OR gate. The three states of the molecular switch are a colorless spiropyran, a purple trans-merocyanine, and its yellow-green protonated form. We have elucidated their structures by X-ray crystallography, (1)H NMR spectroscopy, COSY and NOE experiments, as well as density functional calculations. The three input stimulations controlling the interconversion of the three states of the molecular switch are ultraviolet light, visible light, and H(+). The two outputs are the absorption bands in the visible region of the two colored states of the molecular switch. We have monitored the switching processes and quantified the associated thermodynamic and kinetic parameters with the aid of (1)H NMR and visible absorption spectroscopies.

Temperature dependence of superconductor-correlated metal–superconductor Josephson junctions

Josephson junctions, with the barrier composed of a correlated metal (or insulator) tuned to lie close to the metal–insulator transition, show promise to provide the fastest operating speeds for digital electronics based on rapid single-flux quantum logic. We provide theoretical calculations that indicate that these devices have a small enough temperature derivative of Ic(T) within the junction operating range to allow them to be employed as elements in complex digital circuits.

AN FPGA MOVE GENERATOR FOR THE GAME OF CHESS

This article details the use of an FPGA (Field Programmable Gate Array) to increase the playing strength of the chess-playing program MBChess . The FPGA is a user-reconfigurable logic device well suited to the development of complex digital circuits.

A Single Clocked Adiabatic Static Logic--A Proposal for Digital Low Power Applications

A modified method to construct adiabatic logic is introduced. Advantages of this circuitry over most of the previous ones is that logic behaves in a static mode. In the present research the applicability of a one-phase power clock was studied. The functionality was guaranteed by having the power source frequency much higher than the logic frequency. The new logic gates do not differ much from any standard CMOS logic gates. The only difference is the use of diodes to form logical `1' and `0' states. The static nature of the introduced logic family makes possible to apply the charge recycling technic to other more complex digital circuits and systems. In measurements 77% power saving was achieved compared to a conventional CMOS logic.

A system-level simulation of complex multi-domain microsystems by using analogue hardware description languages

A simulation approach is presented, which permits the simulation of spatially distributed fields with behavioral models of other physical effects and accompanying electronics within a single simulator environment. The final system-level model is a blend of finite-element, analytical, semi-analytical and parametric behavioral models with complex analogue and digital circuit networks. Previously evaluated calculations revealed successful simulation of finite element models with more than 25 000 nodes by using analogue simulators with hardware description language. The relative error of static calculations in comparison with commercial finite element simulators is better than 0.002% and 0.08% for 2D and 3D models, respectively. The results obtained in transient model verification proved the accuracy of the method. The simulation of the flow sensor system, whose functionality is governed by coupled fluidic-thermal-electric domains, is employed to show the feasibility of the method for complex microsystem modeling.

Multi-Gb/s operation of flipped chip MVTL circuits

Development of a reliable flipped chip mounting technique enables demonstration of high speed, complex digital circuits. Flip chip mounting has greatly reduced parasitic inductance compared to conventional wire bonding, and permits remounting of known good die onto multi-chip modules. Superconductive digital circuits have operated to 4.3 Gb/s in our custom test station. The circuit and carrier are fabricated using TRW's foundry process. The chips are flipped onto a superconducting coplanar carrier using a low temperature solder reflow process reported on at this conference. Testing is performed in a multi-GHz, flip contact, variable temperature probe. This test facility is capable of testing circuits to 12 Gb/s. We will describe the operation and performance of our circuits at high bit rates, and design improvements intended to facilitate operation at higher bit rates with improved yield. In addition, we will discuss the use of a logic simulation tool to analyze the output words, and pinpoint the gate or gates that failed to operate properly.

Digital circuit design using FPGAS

Field Programmable Gate Arrays are generic devices that contain a vast number of basic digital components. The interconnections between these components are defined by the user. By specifying these interconnections different digital circuits may be realized. FPGAS are reprogrammable devices, making the change from one digital circuit to another as simple as downloading a new interconnection file. Furthermore the definition of the interconnection file may be carried out at high level machine languages, making the design and debugging of complex digital circuits rather simple. This publication discusses the use of FPGA as an alternate solution to ASICs. A review of the FPGA technology and its impact on the use of ASICs is carried out. This is followed by a projection of the impact of FPGA on digital technology. Finally methods on introducing FPGA technology to in the classroom and its impact on the quality of future engineers in considered. A case study of the FPGA impact on the Computer Engineering Technology Department of the University of Southern Mississippi will be considered.

Integrated Systems [systems on a chip

Integrated Systems are defined as batch-fabricated interconnections of complex digital integrated circuits with analog interface circuits and transducers, such as sensors. By providing the cost, performance and reliability levels of monolithic integration, they offer potential advantages over multi-chip modules assembled with packaging technology. This paper studies the required process technology, as well as design, test and packaging issues, for integrating wide varieties of systems. The goal is to delineate the necessary steps in bringing Integrated Systems to market within a realistic period. With monolithic integration as the ultimate aim, a multi-chip entry point is identified that can start system technology on a learning curve of cost reduction using the same scaling principles that drive integrated circuits. Three challenges to be surmounted are identified in streamlining the I/O's and progressing along a learning curve, namely I/O scaling, I/O loading, and full-functional test. The "composite IC" is the entry point. A large chip, containing only global interconnects and power distribution, acts as a silicon backplane. Subsystem-chips, such as digital microprocessors or sensors, are flip-chip mounted using the accuracy of MEMS processing to fabricate "snap-together" physical and electrical interfaces with high reproducibility. While similar to conventional MCM's, this chip-to-chip connection has few compromises over on-chip connections. By keeping the fabrication responsibility within one organization, just as in monolithic chips, there is no need for incoming inspection. Added ESD protection and test-head loading are avoided on interior nodes by a new intra-factory method of testing.

Modeling digital circuits for troubleshooting

Existing methods for model-based troubleshooting have not previously scaled up to deal with complex digital circuits, in part because traditional circuit models do not represent aspects of the device that troubleshooters consider important. An instruction level simulation of a microprocessor explicitly represents the logic levels present on its external bus at every clock edge, but not the fact that during normal operation those bus signals should be very active. A schematic may represent the connectivity of field replaceable components, but does not show how their combined behavior implements the intentions of the designer. The specifications of a component rarely say how it is likely to fail. This suggests basing troubleshooting on a specialized circuit model that emphasizes such aspects. Although it is beyond current technology to derive such models from circuit schematics automatically, this work shows that these models can make the trouble-shooting of complex circuits feasible. This paper describes an implemented program for troubleshooting complex digital circuits, using a representation that makes explicit their behavior at a high level of temporal abstraction, their physical and functional organization, and the common ways that their components fail.

Understanding single event phenomena in complex analog and digital integrated circuits

Single event phenomena (SEP) responses of complex analog and digital integrated circuits (ICs) cannot be characterized using common (i.e. memory) techniques. An analysis technique for complex SEP response has been developed that allows system analysis for the data in order to increase confidence in their thoroughness. The resulting data are directly applicable to existing orbital error rate codes. The general analysis technique is the main thrust of this study. For a circuit with a complex SEP response, guidelines are established which allow a complete solution to the linear system by establishing relevant error categories, the raw error variables, and a method of error separation. When the data are presented in the framework of a complete linear system, the required independent analysis for system use can proceed with high confidence in the SEP data. The technique is used to analyze the SEP response of an analog-to-digital converter. >

Monolithic integration of a 3-GHz detector/preamplifier using a refractory-gate, ion-implanted MESFET process

High-performance interdigitated metal-semiconductor-metal (IMSM) detectors and photoreceivers have been fabricated using a standard refractory-gate, ion-implanted MESFET process which was also used to fabricate complex digital circuits. A rise time of 110 ps has been observed for a detector-preamplifier combination implying a small-signal bandwidth of about 3 GHz. Detector responsivities as high as 0.45 A/W, and dark currents as low as 5 nA have been observed.

Built-in test for complex digital integrated circuits: B. Konemann, J. Mucha and G. Zwiehoff Fifth Solid State Circuits Conference—ESSCIRC 79, IEE Publn. 178, 89

Built-in test for complex digital integrated circuits: B. Konemann, J. Mucha and G. Zwiehoff Fifth Solid State Circuits Conference—ESSCIRC 79, IEE Publn. 178, 89

Built-in test for complex digital integrated circuits

A method for testing the logic function of complex digital integrated circuits is presented. The extra hardware needed is kept minimal by functional conversion of already existing components (e.g., registers). The feasibility of the proposed method is demonstrated by results from both hardware simulation and logic simulation. The method is based on an adapted version of signature analysis, and on circuit partitioning (the structure of VLSI circuits is assumed to be inherently modular).

Built-in test for complex digital integrated circuits : B. Konemann, J. Mucha and G. Zwiehoff. Fifth Solid State Circuits Conference—ESSCIRC 79, IEE Publn.178, 89

A method is presented for the analysis of track length distributions in mica track detectors and track diameter distributions in glass detectors, produced by the fission fragments of medium mass nuclei. Measured distributions are compared with distributions calculated from trial values for the total kinetic energy release, the center-of-mass motion, and the form of the fragment mass distributions. A FORTRAN computer program has been written that calculates the relevant quantities for the fission process under study and incorporates the characteristics of the stopping process of the fragments. The resulting calculated track length and track diameter distributions show only a moderate sensitivity towards the shape of the fragment mass distribution. A simple fitting procedure is shown to give estimates of the total kinetic energy release as well as of the center-of-mass motions for medium mass fissioning systems. The method is applied to data from the 80 MeV alpha-particle-induced fission of silver, and yields a value for the total kinetic energy release of this system which is higher than present theoretical estimates.

Scratch filter using c.c.d.s

This letter describes the use of charge-coupled devices in the automatic real-time editing of audio signals. A simple semiconductor device is used to replace a number of complex digital circuits.

Noise injection as a measure of semiconductor component performance and degradation

A measurement technique is described which aids the evaluation of the reliability and quality of complex digital integrated circuits. The power or earth connection to the test circuit is modulated with Gaussian noise and the resultant error rate, measured at the output, may be used either to monitor changes occurring in the circuit or to measure its quality. The basic operating principles and the main components of the measurement system are described and theoretical and experimental results are presented which demonstrate the sensitivity of the method and its ability to respond to changes in the internal circuit which are not readily revealed by other terminal measurements.

Distribution function and reliability of complex digital circuits with random inputs

Boolean constants 1 and 0 actually represent two voltage levels A and B. In general, A and B are random variables and hence all inputs and outputs in a digital circuit are random. In this paper a method is presented by which it is possible to derive directly the distribution function for the output of a complex digital circuit without treating every module separately. Examples are Solved to illustrate tho procedure

Reliability of probabilistic logic circuits with random inputs

In a complex digital circuit, every logic module has a probability of malfunctioning. Also every input to a logic circuit has to be treated as a random variable. To evaluate the reliability of a logic circuit, we need to calculate the probability of having the output between two prespecified levels. A method is presented by which it is possible to calculate this probability taking into consideration both the above aspects.