Complementary Metal Oxide Semiconductor Technology Research Articles

Impedance mapping with high-density microelectrode array chips reveals dynamic heterogeneity of in vitro epithelial barriers

Epithelial tissues in vitro undergo dynamic changes while differentiating heterogeneously on the culture substrate. This gives rise to diverse cellular arrangements which are undistinguished by conventional analysis approaches, such as transepithelial electrical resistance measurement or permeability assays. In this context, solid substrate-based systems with integrated electrodes and electrochemical impedance monitoring capability can address the limited spatiotemporal resolution of traditional porous membrane-based methods. This label-free technique facilitates local, continuous, long-term analysis of tissue barrier properties for organ-on-chip applications. Increasing spatial resolution requires small electrodes arranged in a dense array, known as high-density microelectrode arrays (HD-MEAs). Integrated with Complementary Metal Oxide Semiconductor (CMOS) technology for multiplexing and rapid impedance measurements, HD-MEAs can enable high spatiotemporal resolution assessments of epithelial tissues. Here, we used 16,384 CMOS-integrated HD-MEA chip with subcellular-sized electrodes (8 μm diameter, 15 μm pitch, patterned in 16 clusters each consisting of 1024 electrodes in a 32 × 32 matrix) and impedance sensing capability to monitor dynamic evolution of Caco-2 cells, such as their proliferation, barrier formation, and 3D structure development on the chip. Changes in impedance at the selected frequency of 1 kHz (|Z|1kHz) enabled monitoring and analyzing the life cycle of Caco-2 cells grown on the HD-MEA chips (up to + 453% change after 7 days in culture). The |Z|1kHz maps of proliferating Caco-2 cells and the differentiating epithelial tissue developing 3D domes aligned with the corresponding optical images at cellular resolution, which demonstrates the capability of the chip in tracking the dynamic heterogeneity of Caco-2 tissues in a label free and real-time fashion. Importantly, |Z|1kHz maps acquired during chemically induced barrier disruption showed electrodes covered with 3D cell domes experienced a stronger decrease in impedance than those covered with adherent cells (-41% ± sd 10% against -16% ± sd 10%, respectively). This method could thus, in principle, enable detection of tissue barrier disrupting and modifying agents with higher specificity. Epithelial barrier function assays benefit from using HD-MEA impedance sensors due to their increased informativity and resolution, which will be of great value in future organ-on-chip platforms.

Protected memristive implementations of cryptographic functions.

Memristive technology mitigates the memory wall issue in von Neumann architectures by enabling in-memory data processing. Unlike traditional complementary metal-oxide semiconductor (CMOS) technology, memristors provide a new paradigm for implementing cryptographic functions and security considerations. While prior research explores memristors for cryptographic functions and side-channel attack vulnerabilities, our study uniquely addresses memristor-oriented countermeasures. We review different memristive crossbar configurations, implement a four-bit S-box cryptographic function, and analyse memristor-oriented hiding and masking techniques using a self-rectifying passive crossbar. Our findings confirm the efficacy of memristor-oriented hiding techniques but highlight limitations in memristor-oriented masked dual-rail pre-charge logic (MDPL) masking methods. Effective MDPL masking depends on specific power consumption conditions, i.e. the power profile of input data '01' and '10' are not clearly distinguishable from '00' and '11', which, however, are not satisfied across various memristive logic families. Despite passing t-tests, xor4Sbox with CRS-based MDPL masking failed stochastic approaches owing to power consumption differences. Our study prioritizes memristor-oriented countermeasures, advancing the understanding of challenges and opportunities in memristive technology for cryptographic functions.This article is part of the theme issue 'Emerging technologies for future secure computing platforms'.

SiGe semiconductor electronic component: a review on fundamentals and applications

This review addresses the application of silicon-germanium (SiGe) semiconductors as electronic components, highlighting their enhanced electronic and physical properties compared to pure silicon semiconductors. SiGe Semiconductors are widely used in high-performance devices, such as heterojunction bipolar transistors (HBTs) and radio-frequency integrated circuits (RFICs), due to their ability to improve speed, efficiency, and overall device performance. Incoporating Ge into Si increases electron mobility, enabling devices to operate at higher speeds and with lower power consumption, which is crucial for portable and low-power applications. Additionally, SiGe semiconductors are compatible with existing Si semiconductor manufacturing processes, facilitating their integration into complementary metal-oxide semiconductor (CMOS) technologies. Another significant benefit is their improved high-frequency performance, making them suitable for applications such as wireless communications and radar technologies. By varying the Ge composition in SiGe, it is possible to adjust the bandgap and lattice strain, providing flexibility in the design of electronic and optoelectronic devices. These attributes make SiGe semiconductors an ideal choice for a wide range of advanced applications where performance and energy efficiency are essential.

Optimized leakage control in CMOS NAND gates: the in-triggering technique

Abstract Leakage power, now the largest contributor to integrated circuit power consumption, is rising quickly, according to the International Technology Roadmap for Semiconductors (ITRS). As CMOS (complementary metal-oxide semiconductor) technology continues to shrink to deep submicron levels, gate leakage and subthreshold have become important components that contribute to total power dissipation. To address this problem, many methods have been put forth, especially at the circuit level. In 45 nm CMOS, variability and short-channel effects limit noise margins and compromise gate delays, thereby compromising the timing closure and robustness of ultra-low voltage circuits. The resulting supply voltage guardband may reduce energy efficiency in order to achieve a reasonable production yield. Furthermore, the high leakage currents of these technologies decrease energy efficiency when idle intervals are prolonged. In this study, two designs of a novel two-input NAND gate at 45 nm CMOS technology are constructed using eight transistors (8-T). A novel circuit technique named "In-Triggering (INDEP with Bi-Triggering)" is presented in this study with the goal of lowering subthreshold leakage in digital circuits. This method is thoroughly contrasted with other leakage reduction strategies now in use, such as Base, Sleepy LECTOR, LECTOR, INDEP, and Bi-Triggering procedures. Evaluation is done using key performance measures such power-delay product (PDP), latency, subthreshold leakage power, and total power consumption. 45-nm Predictive Technology Models (PTM) with a nominal supply voltage of 1V are used in the investigation. According to our findings, the suggested In-Triggering technique outperforms the conventional NAND gate in terms of speed by 12% and significantly reduces leakage power by up to 56%. Furthermore, compared to the Base, Trig01, and INDEP NAND gates, the method offers mean power savings of 58.8%, 36.1%, and 30.7%, respectively. At supply voltages of 1V, a comprehensive comparison and verification are then conducted utilizing the several proposed and existing methodologies. The effectiveness of the In-Triggering technique in reducing leakage power in CMOS circuits is confirmed by comparing these results to the most well-known design strategies for both active operation and sleep modes.

A Ku-Band Fully Differential Low-Power High-Input P1dB Low-Noise Amplifier.

This paper introduces a Ku-band fully differential low-power high-input 1 dB compression point (P1dB) low-noise amplifier (LNA). A fully differential structure is employed to enhance the input P1dB, common-mode noise rejection, and second harmonic cancellation. The first stage adopts large transistors and is optimized for power consumption and noise figure (NF). The output stage is designed with class AB bias, resulting in improved P1dB, power consumption, and linearity. The proposed two-stage fully differential common-source (CS) LNA was implemented using 65 nm bulk complementary metal oxide semiconductor (CMOS) technology. The fabricated LNA achieved a minimum NF of 2.7 dB at 13.6 GHz. Furthermore, it achieved a maximum gain of 19.92 dB at 12.2 GHz. Additionally, the LNA has an input P1dB of -7.45 dBm and an output power 1 dB compression point (OP1dB) of 10.09 dBm, both measured at 15.6 GHz. The LNA operates with a power consumption of 11 mW at a 1 V supply, and occupies a core size of 0.75 mm × 0.35 mm.

High-Sensitivity, High-Resolution Miniaturized Spectrometers for Ultraviolet to Near-Infrared Using Guided-Mode Resonance Filters.

Miniaturized spectrometers have significantly advanced real-time analytical capabilities in fields such as environmental monitoring, healthcare diagnostics, and industrial quality control by enabling precise on-site spectral analysis. However, achieving high sensitivity and spectral resolution within compact devices remains a significant challenge, particularly when detecting low-concentration analytes or subtle spectral variations critical for chemical and molecular analysis. This study introduces an innovative approach employing guided-mode resonance filters (GMRFs) to address these limitations. Functioning similarly to notch filters, GMRFs selectively block specific spectral bands while allowing others to pass, maximizing energy extraction from incident light and enhancing spectral encoding. Our design incorporates narrow band-stop filters, which are essential for accurate spectrum reconstruction, resulting in improved resolution and sensitivity. Our spectrometer delivers a spectral resolution of 0.8 nm over a range of 370-810 nm. It achieves sensitivity values that are more than ten times greater than those of conventional grating spectrometers during fluorescence spectroscopy of mouse jejunum. This enhanced sensitivity and resolution are particularly beneficial for chemical and biological applications, facilitating the detection of trace analytes in complex matrices. Furthermore, the spectrometer's compatibility with complementary metal oxide semiconductor (CMOS) technology enables scalable and cost-effective production, fostering broader adoption in chemical analysis, materials science, and biomedical research. This study underscores the transformative potential of the GMRF-based spectrometer as an innovative tool for advancing chemical and interdisciplinary analytical applications.

High-speed voltage level-up shifter with wide range conversion for system-on-chip applications

Abstract The purpose of this investigation is to demonstrate a level shifter circuit that enhances voltage switching capacity while simultaneously reducing latency by employing a cascaded current mirror, input, and output inverters. We improved our design using multi-threshold complementary metal-oxide semi-conductor (MTCMOS) technology by adding stackable transistors, super-cutoff mechanisms, and cascaded techniques. The level shifting between voltage ranges of 0.3 V and 2.0 V is accomplished by the proposed level shifter. Our design has been fine-tuned to meet the needs of system-on-chip applications by meticulously optimizing performance characteristics like energy usage, latency, and space utilization. The proposed level shifter has an area of 6.936 μm2 and a power consumption of 17 nW, with a delay of 90.64 ps. The proposed work has been done on the Cadence Virtuoso Tool using 45 nm technology. Our suggested level shifter is more effective than earlier methods in terms of latency and conversion range. In addition to delivering considerable reductions in space and power consumption, the suggested design promises a 50-fold increase in operating speed.

(Invited) Epitaxial Process Development and Challenges for Advanced SiGe BiCMOS

Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) are used daily, mainly in the communication field. Their co-integration with Complementary Metal Oxide Semiconductor (CMOS) technology, i.e. BiCMOS, enables versatile microchips that combine analog, radio-frequency and digital functions. Applications that drive the development of BiCMOS technologies today are Low Earth Orbit (LEO) satellite communications, for which the minimum noise figure of SiGe HBT (NFMIN) between 10 and 30 GHz is one of the most critical figures of merit on the receiver side. It is expected that BiCMOS will play a significant role in the 6G infrastructure, in particular for communications in the D-band spectrum (110-170 GHz), for which the challenge at HBT level is to demonstrate maximum oscillation frequency fMAX > 500 GHz.Benefitting from mature CMOS technologies, the smallest CMOS node used in BiCMOS chips is the 45 nm partially depleted silicon on insulator [1]. STMicroelectronics has been using the 55 nm node since 2014 [2]. These nodes are today sufficient to address the digital content of the targeted circuits, while offering the right performance/cost trade-off. Although the HBT performance depends on lateral scaling too, it is mainly driven by the 1D dopant profile. Multiple Si and SiGe layers are grown by Reduced Pressure-Chemical Vapor Deposition (RP-CVD) epitaxy, defining the core of the device. For a self-aligned architecture such as STMicroelectronics’ EXBIC architecture, four epitaxy steps with different doping levels are required (Fig. 1) [3]. Improvement of key electrical parameters such as NFMIN and fMAX depends on the optimization of these epitaxies.Specifically, the collector epitaxy can be performed by non-selective or selective epitaxy, each with its advantages and drawbacks. Non-selective epitaxy is performed early in the BiCMOS process flow, with no thermal budget impact on the CMOS process. This kind of epitaxy is also cheaper but can cause auto-doping at the epitaxial interface [4] and put constraints on the collector integration, that are solved by the selective epitaxy of the collector. This scheme is used in the latest devices from both STMicroelectronics [3] and GlobalFoundries [5].The transit time of electrons through the base is determined by its thickness and its composition. Significant performance gains have been achieved by switching from pure Si to a graded SiGe base architecture. The bandgap variation due to the graded SiGe composition creates a pseudo-electric field that accelerates the minority carriers transport through the base and limits electron-hole recombination. The addition of carbon into the base limits the boron diffusion and reduces the base thickness, further improving performance. However, only substitutional carbon atoms are required while interstitial carbon atoms must be avoided. The amount of carbon, incorporated in fully substitutional sites, is controlled by the silicon precursor used during RP-CVD epitaxy. At a given temperature it has been shown that a more reactive silicon precursor allows for better substitutional carbon incorporation. By switching from SiH2Cl2 (DCS) to SiH4, the amount of substitutional carbon atoms was increased by 250 % [6]. Following this idea, Si2H6 has been introduced as a silicon precursor to achieve even better substitutional carbon incorporation due to its higher reactivity [7].The emitter process is usually performed by non-selective Si:As epitaxy. This type of epitaxy produces polycrystalline Si:As with a monocrystalline Si:As core above the crystalline base. The emitter resistance can be reduced by processing a fully monocrystalline emitter. A possible solution involving low temperature deposition and solid phase epitaxial regrowth is proposed [8].An overview of the existing problems for each epitaxy step will be given, outlining potential solutions to increase HBT performance to meet customer requirements.[1] J. Pekarik et al., IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 1-4 (2021)[2] P. Chevalier et al., IEEE International Electron Devices Meeting (IEDM),77-79 (2014)[3] A. Gauthier et al., IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 187-190 (2023).[4] P. Jerier and D. Dutartre, J. Electrochem. Soc. 146 ,331 (1999)[5] J. Pekarik et al., ECS Transactions, 109, 141 (2022)[6] F. Brossard et al., International SiGe Technology and Device Meeting (ISTDM), 1-2 (2006)[7] J. Vives et al., ECS Transactions, 109 (4), 237-248 (2022)[8] F. Deprat et al., ECS Transactions, 109, 159 (2022) Figure 1

In-Situ n-Type Doped Carrier-Injection Layers in GeSn Direct Bandgap LEDs for Methane Sensing

GeSn-based group-IV alloys are attracting great attention in the Si photonics community, as they are considered to be compatible with Complementary Metal Oxide Semiconductor (CMOS) technology. Alloying germanium with more than 8% of tin (Sn) results in direct bandgap semiconductors, with some optical gain in devices such as lasers. Recently, room temperature optically pumped lasing was achieved thanks to high Sn content stacks. GeSn alloys can be used for near, short and mid wavelength infra-red spectral range operation, notably for gas detection. Current efforts are focused on electro-optical GeSn IR devices such as light-emitting devices (LEDs), electrically pumped lasers and photodetectors.In this paper, we evaluate the impact of various types of in situ n-type doped carrier injection layers on top of GeSn direct bandgap LEDs. More precisely, we compare the performances of GeSn:P and Ge:P –capped mid IR LEDs. Using reduced pressure chemical vapor deposition and metastable growth conditions (e.g. fast growth rates at low temperature), high crystalline quality GeSn layers were grown on 200 mm diameter Ge-buffered Si(001) wafers (Figure a). In situ n-type doped Ge layers (sample A) and GeSn layers (sample B) were used to inject carriers into direct band gap Ge0.87Sn0.13 active layers beneath (Figure b). I(V) curves (Figure c) and Electro-Luminescence spectra (Figure d) were compared for sample B (GeSn:P) and sample A (Ge:P). Very similar I(V) behaviors were observed under forward bias for both samples. However, a higher dark current was measured under reverse bias for sample B than for sample A. This could be due to a higher number of defects in the thicker capping layer of sample B (240 nm) compared to that of sample A (50 nm). However, a 2-fold increase in the EL signal was obtained for sample B than sample A (Figure d). Temperature dependence electroluminescence measurements and atom probe tomography data will be used to explain the electroluminescence behavior differences between Samples A and B.Finally, even higher Sn content LEDs were fabricated to emit light at 3.3 µm (Figure e). A direct band gap Ge0.846Sn0.154LED (Sample C) with an in situ n-type doped Ge cap was placed in a gas cell filled with diluted methane. Its emission overlapped well with the absorption of methane (Figure f). The methane detection limit of our setup was evaluated (data not shown). To further increase the emitted power of GeSn LEDs, current spreading was studied for different top contact geometries. Emission maps collected by an InSb camera at room temperature showed a definite dependence of light emission on electrical contact geometry (Figure g). Investigations are underway to further increase light extraction from LEDs and improve their performances for use in environmental sensors. Acknowledgement: This work was supported by the European Union’s Horizon 2020 LASTSTEP Project under the grant agreement ID: 101070208, the EDEN Carnot project and the CEA DRF-DRT Phare project. We gratefully acknowledge the clean room staff from LETI and IRIG for their technical support. Figure 1

Reservoir Computing System with Diverse Input Patterns in HfAlO-Based Ferroelectric Memristor.

Ferroelectric memristors, particularly those based on hafnia, are gaining attention as potential candidates for neuromorphic computing. These devices offer advantages over perovskite-based ferroelectric memristors owing to their simpler structures, compatibility with complementary metal-oxide semiconductor technology, and low-power consumption characteristics. Additionally, improvements in ferroelectric memristor's performance, such as enhancing tunneling electro resistance (TER) and polarization retention, can be achieved using methods like aluminum doping and insulating film deposition. In this study, we implement a physical reservoir computing (RC) system utilizing the metal-ferroelectric-insulator-semiconductor-structured ferroelectric memristor based on Al-doped HfO2 as an artificial synapse. Specifically, we ensure the universality and diversity of the system by experimentally demonstrating a robust reservoir layer capable of handling various types of input pulses. To utilize the ferroelectric memristor in the reservoir layer of the RC system, we employ partial polarization switching of ferroelectric materials. We measure the retention loss characteristics of the device for pulse amplitude, interval, and width, and quantify the time constant values by fitting them to a stretched exponential function. Additionally, we validate the suitability of the fabricated device as an artificial synapse by mimicking various short-term plasticity functions of biological synapses. Furthermore, we experimentally demonstrate various applications related to learning and memory of the brain, such as image training and Pavlov's experiment, utilizing the short-term memory characteristics of the fabricated device. Lastly, we evaluate the robustness of the RC system under various input conditions by employing the fabricated device as a reservoir layer.

3D Nano Hafnium‐Based Ferroelectric Memory Vertical Array for High‐Density and High‐Reliability Logic‐In‐Memory Application

AbstractA new type of ferroelectric memory device with high reliability and complementary metal‐oxide‐semiconductor (CMOS) compatibility characteristics is an important condition for achieving integrated memory and computing chips. Here, 3D stacked ferroelectric memory devices based on ferroelectric materials of HfO2 are fabricated. The device exhibits high speed (50 ns), low read voltage (0.5 V), and great reliability with no substantial degradation after 1010 cycles and a 10‐years data retention at 85 °C. The IMP and NAND logic are achieved with stable memory window (>200 mV) across the vertical devices’ interconnection. On this basis, combining with the traditional CMOS logic device, multiple combination logic functions containing NOT, AND, and NOR are achieved by simulation. The collaboration of devices in the vertical direction providing the possibility of combining multi‐bit logic in memory functions and paves the way for the implementation of high‐density, high‐reliability, and low‐energy consumption computing‐in‐memory chips compatible with the CMOS technology.

CMOS Pulse Oximeter

Abstract: This paper presents the design and implementation of a non-invasive pulse oximeter based on Complementary MetalOxide-Semiconductor (CMOS) technology, aimed at enhancing the accuracy and accessibility of blood oxygen saturation measurements. Pulse oximetry is a critical tool in clinical and personal health monitoring, providing vital information about respiratory function. The integration of CMOS technology allows for miniaturization and energy efficiency, facilitating the development of compact, wearable devices capable of continuous monitoring. The proposed system utilizes advanced signal processing techniques, including lock-in detection and dual-wavelength illumination, to improve the reliability of photoplethysmographic (PPG) signal acquisition under various conditions. Experimental validation demonstrates the device's capability to deliver accurate SpO2 readings even in the presence of motion artifacts and ambient light interference. Furthermore, the calibration methods employed ensure that measurements are consistent and precise across different users. By leveraging the advantages of CMOS technology, this study not only highlights the potential for improved patient comfort and compliance but also opens new avenues for the application of pulse oximetry in diverse environments. The findings underscore the effectiveness of CMOS-based pulse oximeters in advancing non-invasive health monitoring solutions, ultimately contributing to enhanced patient care and outcomes.

Performance Analysis of 8x4 Barrel Shifters in CMOS and FINFET Technology

Shifters are essential components in digital circuits, enabling data manipulation and routing for a wide range of computational tasks. This study presents a comprehensive performance analysis of 8x4 barrel shifters implemented in two distinct semiconductor technologies: Complementary Metal-Oxide-Semiconductor (CMOS) and FinFET. This study compares and evaluates the important parameters for these shifters at both technological nodes, such as power consumption. Additionally, we examine the effects of scaling on CMOS barrel shifters. Conversely, FinFET technology, recognized for overcoming certain limitations of CMOS, is assessed for its potential to enhance performance while preserving energy efficiency. Through detailed simulation and analysis, this study offers valuable insights into the benefits and limitations of CMOS and FinFET implementations for 8x4 barrel shifters. The circuit is implemented using Cadence Virtuoso and optimized to leverage the unique features and address the limitations of 45nm CMOS and 22nm FinFET technologies. Furthermore, the study offers recommendations for selecting the appropriate technology based on specific performance criteria and application needs. The findings aim to guide future design decisions and improvements in shifter technology.

Voltage Differencing Buffered Amplifier Realisation Using 32 nm FinFET Technology and Universal Filter Applications

This paper presents high-frequency universal filter applications based on a voltage differential buffered amplifier (VDBA) using 32 nm fin field effect transistor (FinFET) technology. FinFET technology is a promising alternative to complementary metal-oxide-semiconductor (CMOS) technology to avoid the problems caused by the decrease in transistor size as the technology evolves. In addition to the manufacturing process being similar to CMOS technology, FinFET technology offers many advantages, such as reduced short channel effects, higher drain current, reduced static leakage current, faster switching time, lower supply voltage, lower power consumption, and higher efficiency. The VDBA active circuit block, which has high input impedance and low output impedance, is preferred for high-frequency and high-bandwidth applications. It is advantageous to design active filter circuits using VDBA because of its superior features, such as lower power consumption, higher bandwidth, wider range linearity, and the ability to implement the proposed circuits without external resistors. In this study, FinFET-based VDBA and filter application are simulated with the Spice simulation programme using 32 nm PTM technology parameters. Simulation results using 32 nm FinFET technology are compared with those using 0.18 µm TSMC technology. It is concluded that 32 nm FinFET technology reduces power consumption by 98.8 % and increases bandwidth by 145 times. The successful results show that FinFET technology is superior to CMOS technology in analogue circuit design. FinFET-based VDBA circuits and filters will be more advantageous in the design of signal processing and biomedical applications.

Ion-migration-induced synaptic plasticity in high ion-storable fluorine graphdiyne for information processing

Neuromorphic devices encounter constraints associated with complementary metal–oxide–semiconductor technology, such as intricate electronics and high power consumption. Recently, solid polymer electrolytes (SPE) have gained attention in electronic devices for constructing artificial synapses, primarily due to their low-voltage operation enabled by ion-assisted signal transmission. This study presents a two-terminal artificial synapse fabricated using fluorine graphdiyne (F-GDY) synthesized through chemical vapor deposition and ion-doped SPE. The device architecture consists of Au/SPE/F-GDY/Si, which operates by ion migration induced by external potential pulses. Electrical measurements are conducted to depict the synaptic plasticity of the devices. Among devices employing different ion-doped SPEs (Li-SPE, Na-SPE, K-SPE, and Ca-SPE), the one utilizing Li-SPE demonstrates the highest synaptic weight. This is attributed to the superior Li+ ion storage capacity of F-GDY. Hence, Li-SPE/F-GDY was chosen for in-depth examinations of synaptic activity presenting long-term potentiation, short-term depression, and pair-pulse facilitation. The device has good durability and stability and can respond to low action potential with power consumption at the pJ level. Furthermore, Modified National Institute of Standards and Technology simulations reveal its learning and pattern recognition capability with 91.3 % accuracy after 10 training epochs. Finally, flexible substrate-based SPE/F-GDY devices integrated with gate electrodes were fabricated to record physiological signals, showing promise for in-sensing applications. This work shows the potential of F-GDY/Li-SPE devices for low-power neuromorphic computing, though real-time parallel processing and multimodal integration (e.g., visual, auditory) remain unexplored. Even so, the biocompatibility and efficient ion-assisted transmission of F-GDY suggest promising future applications in these areas.

Efficient quantum-dot adder optimisation and analysis for future circuits

ABSTRACT In recent years, the rapid scaling of transistors has necessitated the exploration of advanced alternatives to Complementary metal oxide semiconductor(CMOS) technology for future progress. Quantum-dot cellular automata(QCA) technology has emerged as a promising solution, offering highly dense, high-speed, and low-power circuits. Among the critical digital building blocks, adder circuits play a crucial role in arithmetic and logic units. Consequently, optimising these circuits in terms of area, delay, and quantum cost is essential for the development of efficient designs. This paper presents effective multi-layer n-bit ripple carry adder(RCA) circuits, utilising full adder(FA) circuit. The outputs are generated in distinct layers and verified using the QCADesigner-Ev2.2 tool with bi-stable and coherence vector energy setups, employing Euler and Runge-Kutta methods.Additionally, the proposed designs are evaluated for various design metrics at three different scale factors(1,0.8889,and 0.7778), corresponding to cell sizes of 18 × 18 nm , 16 × 16 nm , and 14 × 14 nm respectively. The temperature’s impact on the average output polarisation of the FA is explored. The research demonstrates an n-bit-RCA surpassing existing designs with cost optimisations of 89.5%, 86%, and 90.3% for 4-bit,8-bit and 16-bit circuits, respectively. The paper also provides a thorough energy dissipation analysis for the proposed adder design.

Design of SRAM cell using an optimized D-latch in quantum-dot cellular automata (QCA) technology

A newer nanoscale technology called quantum-dot cellular automata (QCA) has been used by researchers to design digital circuits in place of the more traditional complementary metal–oxide semiconductor (CMOS) technology. This recent development in the technology change is due to the problems faced by CMOS technology in terms of power consumption and physical limitations. The advantages of QCA technology over CMOS technology are high density, low power consumption, high-speed operation, and less footprint area. This research provides a novel circuit for D-latch and static random access memory (SRAM) cells based on QCA technology. Initially, a D-latch circuit is proposed with a layout area of 0.01 μm2, a 0.5 clock cycle delay (latency), and a cell count of 18 QCA cells. Furthermore, an SRAM cell is proposed using the same D-latch circuit, which uses cell counts of 26 QCA cells and contributes to a layout area of 0.02 μm2 with a 0.75 clock cycle delay (latency). It is observed that our proposed circuits have a smaller layout area, fewer QCA cell counts, and a lower clock cycle delay (latency) than existing circuits.

ITO-Based Electrically Tunable Metasurface for Active Control of Light Transmission.

In recent years, the rapid development of dynamically tunable metasurfaces has provided a new avenue for flexible control of optical properties. This paper introduces a transmission-type electrically tunable metasurface, employing a series of subwavelength-scale silicon (Si) nanoring structures with an intermediate layer of Al2O3-ITO-Al2O3. This design allows the metasurface to induce strong Mie resonance when transverse electric (TE) waves are normally incident. When a bias voltage is applied, the interaction between light and matter is enhanced due to the formation of an electron accumulation layer at the ITO-Al2O3 interface, thereby altering the resonance characteristics of the metasurface. This design not only avoids the absorption loss of metal nanostructures and has a large modulation depth, but also shows compatibility with complementary metal oxide semiconductor (CMOS) technology.

Recent trends in neuromorphic systems for non-von Neumann in materia computing and cognitive functionalities

In the era of artificial intelligence and smart automated systems, the quest for efficient data processing has driven exploration into neuromorphic systems, aiming to replicate brain functionality and complex cognitive actions. This review assesses, based on recent literature, the challenges and progress in developing basic neuromorphic systems, focusing on “material-neuron” concepts, that integrate structural similarities, analog memory, retention, and Hebbian learning of the brain, contrasting with conventional von Neumann architecture and spiking circuits. We categorize these devices into filamentary and non-filamentary types, highlighting their ability to mimic synaptic plasticity through external stimuli manipulation. Additionally, we emphasize the importance of heterogeneous neural content to support conductance linearity, plasticity, and volatility, enabling effective processing and storage of various types of information. Our comprehensive approach categorizes fundamentally different devices under a generalized pattern dictated by the driving parameters, namely, the pulse number, amplitude, duration, interval, as well as the current compliance employed to contain the conducting pathways. We also discuss the importance of hybridization protocols in fabricating neuromorphic systems making use of existing complementary metal oxide semiconductor technologies being practiced in the silicon foundries, which perhaps ensures a smooth translation and user interfacing of these new generation devices. The review concludes by outlining insights into developing cognitive systems, current challenges, and future directions in realizing deployable neuromorphic systems in the field of artificial intelligence.

Wafer-Scale Atomic Layer-Deposited TeOx/Te Heterostructure P-Type Thin-Film Transistors.

There is an increasing demand for p-type semiconductors with scalable growth, excellent device performance, and back-end-of-line (BEOL) compatibility. Recently, tellurium (Te) has emerged as a promising candidate due to its appealing electrical properties and potential low-temperature production. So far, nearly all of the scalable production and integration of Te with complementary metal oxide semiconductor (CMOS) technology have been based on physical vapor deposition. Here we demonstrate wafer-scale atomic layer-deposited (ALD) TeOx/Te heterostructure thin-film transistors with high uniformity and integration compatibility. The wafer-scale uniformity of the film is evidenced by spatial Raman mappings and statistical electrical analysis. Furthermore, surface accumulation-induced good ohmic contact has been observed and explained by the unique band alignment of the charge neutrality level inside the Te valence band. These results demonstrate ALD TeOx/Te as a promising p-type semiconductor for monolithic three-dimensional integration in BEOL CMOS applications incorporated with well-established n-type ALD oxide semiconductors.