Complementary Metal Oxide Semiconductor Substrate Research Articles

Design of on‐chip antennas for THz detector and source in CMOS (Invited paper)

AbstractDifferent on‐chip antennas in Complementary Metal‐Oxide‐Semiconductor (CMOS) technology for THz detector and source are proposed. Firstly, the size of these antennas is estimated with an equivalent CMOS substrate model. Finally, through electromagnetic simulation, the structure optimised and slotted the on‐chip antenna to realise multi‐band detection, miniaturised detection, and miniaturised source. For the THz detector, multi‐band antennas with a dual‐ring structure and miniaturised antennas with circular and diamond structures are designed. At the frequency of 300, 600, and 800 GHz, the gain of the ring antennas is 5.7, 7.2, and 7.2 dBi, respectively. The gain of the circular and diamond antenna is 5.3 and 5.96 dBi at 300 GHz. For the THz source, rectangular‐slot and T‐slot antennas are designed at the frequency of 300 GHz and the gain of the rectangular‐slot and T‐slot antennas is 2.92 and 3.87 dBi, respectively. Multi‐band antennas and miniaturised antennas effectively save the occupation area and improve the performance of the THz system. The effectiveness of antennas is verified by the measurement of the detector and the source, which indicates that the proposed on‐chip antennas have potential prospects for CMOS THz applications.

Soliton frequency comb generation in CMOS-compatible silicon nitride microresonators

The monolithic integration of soliton microcomb devices with active photonic components and high-frequency electronics is highly desirable for practical applications. Among many materials, silicon nitride ( SiN x ) waveguide layers prepared by low-pressure chemical vapor deposition (LPCVD) have been the main platform for on-chip optical frequency comb generation. However, the high temperatures involved in LPCVD render it incompatible as a back-end process with complementary metal oxide semiconductor (CMOS) or active III-V compound semiconductor fabrication flows. We report the generation of coherent soliton frequency combs in micro-ring resonators fabricated in deuterated silicon nitride ( SiN x : D ) waveguides with a loss of 0.09 dB/cm. Deposited at 270°C by an inductance-coupled plasma chemical vapor deposition (ICP-CVD) process, the material preparation and fabrication flow are fully CMOS-compatible. These results enable the integration of silicon-nitride-based optical combs and photonic integrated circuits (PICs) on prefabricated CMOS and/or III-V substrates, therefore marking a major step forward in SiN x photonic technologies.

Hybrid image sensor of small molecule organic photodiode on CMOS \u2013 Integration and characterization

Organic photodiodes (OPDs) for its interesting optoelectronic properties has the potential to be utilized with complementary metal-oxide-semiconductor (CMOS) circuit for imaging, automotive, and security based applications. To achieve such a hybrid device as an image sensor, it is imperative that the quality of the OPD remains high on the CMOS substrate and that it has a well-connected optoelectronic interface with the underneath readout integrated circuit (ROIC) for efficient photogeneration and signal readout. Here, we demonstrate seamless integration of a thermally deposited visible light sensitive small molecule OPD on a standard commercial CMOS substrate using optimized doped PCBM buffer layer. Under a standard power supply voltage of 3 V, this hybrid device shows an excellent photolinearity in the entire bias regime, a high pixel sensitivity of 2 V/Lux.sec, a dynamic range (DR) of 71 dB, and a low dark leakage current density of 1 nA/cm2. Moreover, the integrated OPD has a minimum bandwidth of 400 kHz. The photoresponse nonuniformity being only 1.7%, achieved under research lab conditions, strengthens the notion that this fully-CMOS compatible technology has the potential to be applied in high-performance large-scale imaging array.

(Invited) Adhesive Wafer Bonding for Heterogeneous System Integration

Heterogeneous integration of micro- and nano-electromechanical systems (MEMS, NEMS) and photonic devices on top of integrated circuits (ICs) is an emerging technology that will lead to highly compact devices combining traditional ICs with advanced sensors and actuators. Different components, such as MEMS, photonic devices, and complementary metal oxide semiconductor (CMOS) circuits are fabricated on separate substrates and subsequently joined into one single substrate by wafer bonding [1,2]. This enables the integration of high-performance MEMS, NEMS, and photonic devices made of materials such as mono-crystalline silicon, germanium, III–V materials, piezoelectric materials, shape memory alloys (SMAs), carbon nanotubes (CNT), or nanowires directly on top of ICs, which is otherwise not possible. We review heterogeneous integration approaches for various MEMS, NEMS, and photonics systems based on layer transfer by adhesive wafer bonding. The main advantages of adhesive wafer bonding are the low bonding temperatures (20 - 450°C), its insensitivity to wafer surface topology, the compatibility with standard CMOS wafers, and the ability to join practically any wafer materials [3]. Adhesive wafer bonding does not require special wafer surface treatments, such as planarization or excessive cleaning, and therefore, offers a simple and cost-effective transfer process. Layer transfer by adhesive wafer bonding consists of several steps. First, the donor wafer, containing the layer to be transferred, is aligned to the target wafer (e.g. CMOS wafer) and bonded using an intermediate polymer adhesive. Second, the bulk material (e.g. Si substrate) of the donor wafer is sacrificially etched while the transferred layer remains on the target wafer of top of the polymer layer. The transferred layer can subsequently be further processed using conventional process steps to create the desired devices. Compatible processes include structuring and etching of the transferred layer, material deposition such as chemical and physical vapour deposition (CVD, PVD), ion implantation, and annealing amongst others. These processes can be used to create electrical, mechanical, and photonic devices and electrical interconnections between the transferred layers and the underlying substrate (vias). Using adhesive bonding with an intermediate polymer further offers highly selective and controlled sacrificial release etching capabilities in O2 plasma. This provides a simple approach for realizing free-standing MEMS and NEMS structures without wet etching and critical point drying (CPD), thus increasing manufacturing yield and reducing fabrication complexity. Lastly, the presented heterogeneous integration approach is compatible with pre-structuring of the target substrates, as well as of the transfer layer. Thus, it is possible to integrate not only layers of high-performance materials, but pre-processed devices and systems. We illustrate the versatility of adhesive wafer bonding for heterogeneous integration with different application examples of MEMS and optical systems integrated onto various target substrates. Each example requires a slightly different heterogeneous integration approach. A suspended Si/SiGe quantum-well infrared microbolometer array was integrated on top of a CMOS substrate by adhesive transfer bonding of the Si/SiGe thermistor layer and subsequent patterning of the bolometer array [4]. Since the bolometer pixels needed to be suspended, Ni pillars were formed and the polymer adhesive was sacrificially removed to free-etch the bolometer pixels. The Ni pillars provide both electrical connection to the underlying CMOS circuits and mechanical support for the suspended bolometer pixels. For the integration of nano-electromechanical (NEM) switches for ultra-low power computing applications, TiW vias were used as electrical interconnects. In order to achieve short signal path lengths and thereby increase the performance and energy efficiency of the circuits, an ultra-thin adhesive bonding layer of just 200 nm was used. In optical systems that don’t require electrical interconnections, the polymer adhesive itself can be used as mechanical support. Finally, the capability for multiple layer transfer steps was demonstrated by fabricating hidden hinge micromirror arrays [5]. In this approach, a layer of mono-crystalline silicon was transferred onto the target wafer and the mirror hinges were subsequently patterned in this layer. Pillars extending from the hinge layer to the target substrate were formed, but the polymer adhesive was not removed at this stage. Instead, a second mono-crystalline silicon layer was transferred on top of the hinge layer using adhesive bonding. The mirrors are then formed in this second transferred layer. Pillars connecting the mirrors to the hinges were formed and finally both polymer adhesive layers were sacrificially removed in O2-plasma, thus, creating free-standing micromirrors. In conclusion, the flexibility to precisely control the thickness of the adhesive polymer layers and selectively remove it makes adhesive wafer bonding a highly versatile approach for heterogeneous integration of a large variety of MEMS and photonic applications. Figure 1

Deuterated silicon nitride photonic devices for broadband optical frequency comb generation.

We report and characterize low-temperature, plasma-deposited deuterated silicon nitride films for nonlinear integrated photonics. With a peak processing temperature less than 300°C, it is back-end compatible with complementary metal-oxide semiconductor substrates. We achieve microresonators with a quality factor of up to 1.6×106 at 1552nm and >1.2×106 throughout λ=1510-1600 nm, without annealing or stress management (film thickness of 920nm). We then demonstrate the immediate utility of this platform in nonlinear photonics by generating a 1THz free-spectral-range, 900nm bandwidth modulation-instability microresonator Kerr comb and octave-spanning, supercontinuum-broadened spectra.

3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer.

This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS) with capacitive sensing circuits on a low temperature cofired ceramic (LTCC) interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D)-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively.

Pulsed laser deposition of piezoelectric lead zirconate titanate thin films maintaining a post-CMOS compatible thermal budget

Integration of lead zirconate titanate (Pb[Zrx,Ti1-x]O3 – PZT) thin films on complementary metal-oxide semiconductor substrates (CMOS) is difficult due to the usually high crystallization temperature of the piezoelectric perovskite PZT phase, which harms the CMOS circuits. In this work, a wafer-scale pulsed laser deposition tool was used to grow 1 μm thick PZT thin films on 150 mm diameter silicon wafers. Three different routes towards a post-CMOS compatible deposition process were investigated, maintaining a post-CMOS compatible thermal budget limit of 445 °C for 1 h (or 420 °C for 6 h). By crystallizing the perovskite LaNiO3 seed layer at 445 °C, the PZT deposition temperature can be lowered to below 400 °C, yielding a transverse piezoelectric coefficient e31,f of −9.3 C/m2. With the same procedure, applying a slightly higher PZT deposition temperature of 420 °C, an e31,f of −10.3 C/m2 can be reached. The low leakage current density of below 3 × 10−6 A/cm2 at 200 kV/cm allows for application of the post-CMOS compatible PZT thin films in low power micro-electro-mechanical-systems actuators.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

Wafer-Level Vacuum Packaging Enabled by Plastic Deformation and Low-Temperature Welding of Copper Sealing Rings With a Small Footprint

Wafer-level vacuum packaging is vital in the fabrication of many microelectromechanical systems (MEMS) devices and enables significant cost reduction in high-volume MEMS production. In this paper, we propose a low-temperature wafer-level vacuum packaging method based on plastic deformation and low-temperature welding of copper sealing rings with a small footprint. A device wafer with copper ring structures and a cap wafer with corresponding metalized grooves are placed inside a vacuum chamber and pressed together at a temperature of 250 °C, resulting in low-temperature welding of the copper, and thus, hermetic sealing of the cavities enclosed by the sealing rings. The vacuum pressure inside the fabricated cavities 146 days after bonding was measured using residual gas analysis to be as low as $2.6\times 10^{-2}$ mbar. Based on this value, the leak rate is calculated to be smaller than $ {3.6}\times {10}^{-16}$ mbarL/s using the most conservative assumptions, demonstrating the excellent hermeticity of the seals. Shear testing was used to demonstrate that the seals are mechanically stable with over 90 MPa in shear strength for $5.2~\mu \text{m}$ -high Cu sealing rings with widths down to $8~\mu \text{m}$ . The reported method is potentially compatible with complementary metal-oxide-semiconductor (CMOS) substrates and may be applied to vacuum packaging of 3-D heterogeneously integrated MEMS on state-of-the-art CMOS substrates. [2016-0252]

Electromagnetic simulation modeling of silicon substrate for 60 GHz on-chip differential-feed dipole antenna

A 60 Gigahertz (GHz) on-chip differential-feed dipole antenna integrated in a 65 nm complementary metal oxide semiconductor (CMOS) technology is investigated by simulation and measurement. It was found that it is important to model lossy thin well layer on the surface of CMOS substrate. Simulated frequency characteristic of scattering parameters agreed well with measured one. The simulated radiation efficiency was 3.4%. The loss factor was estimated by electromagnetic simulation, and it was found that low radiation efficiency was mainly due to the existence of the lossy layer and high conductivity of 10 S/m of silicon substrate.

Multilayer bonding using a conformal adsorbate film (CAF) for the fabrication of 3D monolithic microfluidic devices in photopolymer

Reliable microfabrication processes and materials compatible with complementary metal-oxide semiconductor (CMOS) technology are required by industry for the mass production of complex and highly miniaturized lab-on-a-chip systems. Photopolymers are commonly used in the semiconductor industry, and are suitable for the integration of multilayer structures onto CMOS substrates. This paper describes a novel photopolymer bonding process compatible with CMOS technology for the fabrication of three-dimensional monolithic microfluidic devices. The process consists of the formation of a conformal adsorbate film (CAF) approximately 15 nm thick on a patterned photopolymer layer (KMPR), thereby increasing the number of open polymer chains at the bonding interface and acting as an ultra-thin adhesive layer. This thin adhesive layer is made of the same photopolymer as the microfluidic structures, but has a substantially lower crosslinking density so it will be able to make better bonds during a thermocompressive bonding step. This CAF treatment substantially improves the bonding yield between two patterned and previously crosslinked photopolymer layers because both optimum structure strength (to resist deformation during bonding) and bonding strength from epoxy crosslinking can be achieved. We demonstrate high bonding yields of up to 99% of the useful area of the substrate after three successive bonding steps. With this technique, up to six layers have been bonded in a single device. Unlike previously reported methods the quality of bonding is mostly decoupled from soft-bake parameters and crosslinking level of the previously patterned layers. Three differentbonding processes were characterized to describe the bonding mechanism and the differences between the presented method and the partial-crosslinking bonding method. Capillary filling experiments were performed in microchannels of multilayer structures built with the CAF technique, without any observable leakage between layers.

Hybrid carbon nanotube-silicon complementary metal oxide semiconductor circuits

A hybrid technology is presented that combines carbon nanotube field-effect transistors (CNFET) with conventional, silicon-based complementary metal oxide semiconductor (CMOS) technology. The fabrication involves the chemical vapor deposition growth and optical characterization of carbon nanotubes, which are then transferred with lithographic precision onto a commercially fabricated CMOS substrate. In this manner, CNFET devices are fabricated on top of the interconnection network of the CMOS chip, providing a three-dimensional integration of active devices, “sandwiching” wiring, and passives. As a demonstration of this approach, a simple hybrid CNFET/CMOS inverter is fabricated and tested.

CMOS Active Bandpass Filter Using Compacted Synthetic Quasi-TEM Lines at $C$-Band

This paper presents a fully monolithic transmission-line-based active bandpass filter (BPF) fabricated in a 0.18-mum standard complementary metal-oxide-semiconductor (CMOS) technology. The half-wavelength resonators are realized by synthetic quasi-TEM complementary conducting-strip transmission lines (CCS TLs). To lower the insertion loss of the BPF, the differential nMOS cross-coupled pairs are combined with the parallel resonators. Besides, the active devices and CCS TLs are vertically integrated on the standard CMOS substrate. The Q-enhanced resonator, which is comprised of a CCS TL and an nMOS cross-coupled pair, is theoretically investigated. Simulation results indicate that the Q factor of the resonator can be increased from 3.4 to 84.0 at 6.53 GHz. Additionally, the prototype of the second-order BPF occupies an area of 1230 mumtimes880 mum, and the measured results demonstrate that the center frequency is 6.02 GHz with a bandwidth of 1.14 GHz. The P1dB and insertion loss are -15.2dBm and 2.2 dB, respectively, when the BPF consumes 3.0 mA from a 1.8-V supply. A two-port noisy network is also reported to examine the noise figure (NF) of the proposed BPF. Theoretical results reveal that the NF is 11.38 dB at 6.0 GHz, with a difference of less than 7.2% among the measured data

Behavior of Nano-N-Channel Metal–Oxide–Semiconductor Off-State Leakage Currents

In this paper, leakage current behavior is discussed, particularly in the off state of nano-N-channel metal–oxide–semiconductor (NMOS) devices. In our experimental results, we observed a special phenomenon in the off-state I–V (off-current components vs VD) curves. We propose a new model named the gate current induced punch-through (GCIP) model, which is discussed in detail to explain this phenomenon. As the complementary metal–oxide–semiconductor (CMOS) device dimensions are being scaled down to the nano-scale level, the gate oxide thickness is becoming significantly thinner than in any other previously produced devices. The use of ultrathin gate oxide induces an off-state gate leakage current which is not neglect in the gate terminal, and possibly causes the generation of electron-hole pairs in the CMOS substrate. The avalanche effect on electron-hole pair generation finally causes the device punch-through. This punch-through phenomenon is induced by the gate tunneling current, and therefore we named it the GCIP model.