Power Complementary Metal Oxide Semiconductor Research Articles

A Rail-To-Rail and Low Offset Novel Strongarm Comparator Circuit for Low Power Data Converter Architectures

With the rapid improvements in the design of advanced high performance communication receivers, hand-held electronic devices are in widespread usage for some time. These devices facilitate high speed and secured access to internet data. The demand for realizing a smart and better usage experience puts forth strict requirements on the design aspects of next-generation high speed low power complementary metal oxide semiconductor (CMOS) receiver design. One of the major modules in the implementation of high speed low power CMOS receiver device is the analog to digital converter (ADC) architecture. In the process of conversion from analog to digital signals, Quantization and sampling operations are vital and are realized using comparator circuits. The comparator design has a significant role in the design of data converter architecture. Several comparator architectures exist, but StrongARM topology is discussed and implemented in this work due to its negligible static power dissipation and rail to rail output voltages. The proposed novel comparator architecture is designed and simulated in 90nm CMOS process using Cadence Virtuoso tool and operated at supply voltage of VDD=1.5V, a clock frequency of 250MHz. Compared to the previous designs, the energy delay product was reduced by 8% which is an important observation to be observed for use in wireless sensor node applications.

Ultra-wideband CMOS power amplifier for wireless body area network applications: a review

<span lang="EN-US">A survey on ultra-wideband complementary metal-oxide semiconductor (CMOS) power amplifiers for wireless body area network (WBAN) applications is presented in this paper. Formidable growth in the CMOS integrated circuits technology enhances the development in biomedical manufacture. WBAN is a promising mechanism that collects essential data from wearable sensors connected to the network and transmitted it wirelessly to a central patient monitoring station. The ultra-wideband (UWB) technology exploits the frequency band from 3.1 to 10.6 GHz and provides no interference to other communication systems, low power consumption, low-radiated power, and high data rate. These features permit it to be compatible with medical applications. The demand target is to have one transceiver integrated circuit (IC) for WBAN applications, consequently, UWB is utilized to decrease the hardware complexity. The power amplifier (PA) is the common electronic device that employing in the UWB transmitter to boost the input power to the desired output power and then feed it to the antenna of the transmitter. The advance in the design and implementation of ultra-wideband CMOS power amplifiers enhances the performance of the UWB-transceivers for WBAN applications. A review of recently published CMOS PA designs is reported in this paper with comparison tables listing wideband power amplifiers' performance.</span>

Computer Vision-based Monitoring Method for Differential Settlement of Shield Tunnels

Shield tunnels in soft soils are inevitably subject to large differential settlement during construction and long-term operation, which can lead to various diseases and then impair structural safety and durability. Due to the inefficiency of traditional inspection methods, timely and accurate monitoring methods are necessary to ensure the safe operation and long-term maintenance of tunnels. In this study, a computer vision-based monitoring method for differential settlement of shield tunnels was developed and implemented. The monitoring area is located in an interval tunnel of a subway line in Shanghai during the freezing construction of its side channel. The influence of camera position’s micro-change was considered. The field equipment mainly consists of high-resolution industrial CMOS (complementary metal oxide semiconductor) digital camera sets, LED (light emitting diode) lights and power modules. The differential settlement relative to datum points are obtained and vertical displacement of one ring acquired by total station is compared with the proposed method to verify the feasibility of the monitoring system. The results indicate that the monitoring system is reliable and can be further applied.

Three-Stacked CMOS Power Amplifier to Increase Output Power With Stability Enhancement for mm-Wave Beamforming Systems

In this study, an mm-wave band complementary metal–oxide–semiconductor (CMOS) power amplifier (PA) with a two-stage differential structure was designed. An analysis of the designed PA is presented and a new structure is proposed to eliminate the possibility of oscillation in the PA, which has high gain and high output power. The designed driver stage consists of a pair of cascode amplifiers and can be advantageously applied in beamforming systems as the PA phase is converted to 0 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> /180 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> with the on/off of a common-gate (CG) bias voltage. The power stage was designed with a three-stacked structure to obtain a high output power. The stability was improved using RC and capacitive feedbacks in the power stage. We implemented the PA using the 65-nm RF CMOS process. The designed PA used supply voltages of 2.0 and 3.3 V for the driver and power stages, respectively, and its saturated output power was measured as 24.7 dBm at 22.0 GHz. In this case, P <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{1\,dB}}$</tex-math> </inline-formula> was 20.6 dBm and the peak power added efficiency (PAE) was 26.0%.

Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique

In this article, the design, fabrication and characterization of silicon carbide (SiC) complementary-metal-oxide-semiconductor (CMOS)-based integrated circuits (ICs) are presented. A metal interconnect strategy is proposed to fabricate the fundamental N-channel MOS (NMOS) and P-channel MOS (PMOS) devices that are required for the CMOS circuit configuration. Based on the mainstream 6-inch SiC wafer processing technology, the simultaneous fabrication of SiC CMOS ICs and power MOSFET is realized. Fundamental gates, such as inverter and NAND gates, are fabricated and tested. The measurement results show that the inverter and NAND gates function well. The calculated low-to-high delay (low-to-high output transition) and high-to-low delay (high-to-low output transition) are 49.9 and 90 ns, respectively.

Investigation of the Specification Degradation Mechanism of CMOS Power Amplifier under Thermal Shock Test.

To investigate the critical specifications of a power amplifier (PA) under rapidly changing temperature conditions, we fabricated and tested a 0.3–1.1 GHz complementary metal–oxide–semiconductor (CMOS) PA under thermal shock tests. The results show that high- and low-temperature shocks can accelerate the degradation of critical specifications of PAs and that the critical specifications of PAs degrade with the increasing number of shocks. The main reason for the degradation of critical specifications of PAs with increasing thermal shock tests is the mismatch of thermal expansion coefficients of printed circuit boards (PCB) with FR-4 as a substrate. The results of this paper can provide a reference for the development of temperature-robust PAs design guidelines for the implementation of temperature-robust PAs using low-cost silicon technology.

Impact of temperature on radio frequency/linearity and harmonic distortion characteristics of Ge multi‐channel fin shaped field‐effect transistor

This dissertation demonstrates the reliability issues associated with the temperature of Ge multi-channel fin shaped field-effect transistor (Mch-FinFET). Temperature dependence on short channel effectss such as threshold voltage (Vth), sub-threshold swing (SS), and switching ratio are observed. The variation in temperature on various important radio frequency (RE)/analog, linearity, and harmonic distortion characteristics are studied and analyzed over a wide range of temperatures (300–500 K). The simulation study revealed that Mch-FinFET devices exhibit 61.6% improvement in ION with minimum SS value. The improvement of SS, switching ratio and Vth can be observed with temperature fall. The enhancement in performance of various RF/analog attributes such transconductance, device efficiency, transconductance frequency product, gain frequency product, cut-off frequency, and intrinsic gain with lowering of temperature. However, Mch-FinFET device provides a significant improvement of higher-order current and voltage intercept points such as IIP3, VIP2, VIP3, and 1 dB compression point with lesser harmonic distortion such as HD2, HD3, and THD at elevated temperature. The superior efficiency of DC and RF/analog attributes, greater linearity, and minor harmonic distortion performance of Mch-FinFET make it more considerable to design low power Complementary metal–oxide–semiconductor (CMOS) circuits.

A fully matched dual stage CMOS power amplifier with integrated passive linearizer attaining 23 db gain, 40% PAE and 28 DBM OIP3

PurposeThe purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA).Design/methodology/approachThe linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize the effect of Cgs capacitance through the generation of opposite phase response at the main amplifier. The inductor-less output matching network presents an almost lossless output matching network which contributes to high gain, PAE and output power. The linearity performance is improved without the penalty of power consumption, power gain and stability.FindingsWith this topology, the PA delivers more than 20 dB gain for the Bluetooth Low Energy (BLE) Band from 2.4 GHz to 2.5 GHz with a supply headroom of 1.8 V. At the center frequency of 2.45 GHz, the PA exhibits a gain of 23.3 dB with corresponding peak PAE of 40.11% at a maximum output power of 14.3 dBm. At a maximum linear output power of 12.7 dBm, a PAE of 37.3% has been achieved with a peak third order intermodulation product of 28.04 dBm with a power consumption of 50.58 mW. This corresponds to ACLR of – 20 dBc, thus qualifying the PA to operate for BLE operation.Practical implicationsThe proposed technique is able to boost up the efficiency and output power, as well as linearize the PA closer to 1 dB compression point. This reduces the trade-off between linear output power and PAE in CMOS PA design.Originality/valueThe proposed CMOS PA can be integrated comfortably to a BLE transmitter, allowing it to reduce the transceiver’s overall power consumption.

K-Band Hetero-Stacked Differential Cascode Power Amplifier with High Psat and Efficiency in 65 nm LP CMOS Technology

A K-band complementary metal-oxide-semiconductor (CMOS) differential cascode power amplifier is designed with the thin-oxide field effect transistor (FET) common source (CS) stage and thick-oxide FET common gate (CG) stage. Use of the thick-oxide CG stage affords the high supply voltage to 3.7 V and enables the high output power. Additionally, simple analysis shows that the gain degradation due to the low cut-off frequency of the thick-oxide CG FET can be compensated by the high output resistance of the thick-oxide FET if the inter-stage node is neutralized. The measured results of the proposed power amplifier demonstrate the saturated output power of the 23.3 dBm with the 31.3% peak power added efficiency (PAE) at 24 GHz frequency. The chip is fabricated in 65-nm low power (LP) CMOS technology and the chip size including all pads is 700 μm × 630 μm.

Optimized Design of Low Power Complementary Metal Oxide Semiconductor Low Noise Amplifier for Zigbee Application

An optimized high gain low power low noise amplifier (LNA) is presented using 90 nm CMOS process at 2.4 GHz frequency for Zigbee applications. For achieving desired design specifications, the LNA is optimized by particle swarm optimization (PSO). The PSO is successfully implemented for optimizing noise figure (NF) when satisfying all the design specifications such as gain, power dissipation, linearity and stability. PSO algorithm is developed in MATLAB to optimize the LNA parameters. The LNA with optimized parameters is simulated using Advanced Design System (ADS) Simulator. The LNA with optimized parameters produces 21.470 dB of voltage gain, 1.031 dB of noise figure at 1.02 mW power consumption with 1.2 V supply voltage. The comparison of designed LNA with and without PSO proves that the optimization improves the LNA results while satisfying all the design constraints.

A 23.3 dBm CMOS power amplifier with third-order gm cancellation linearization technique achieving OIP3 of 34 dBm

PurposeThe purpose of this paper is to implement a highly linear 180 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) to meet the stringent linearity requirement of an long term evolution (LTE) signal with minimum trade-off to power added efficiency (PAE).Design/methodology/approachThe CMOS PA is designed in a cascaded dual-stage configuration comprises a driver amplifier and a main PA. The gate voltage (VGS) of the driver amplifier is tuned to optimize its positive third-order transconductance (gm3) to be canceled with the main PA’s fixed negative gm3. The gm3 cancellation between these stages mitigates the third-order intermodulation product (IMD3) that contributes to enhanced linearity.FindingsFor driver’s VGS of 0.82 V with continuous wave signal, the proposed PA achieved a power gain of 14.5 dB with a peak PAE of 31.8% and a saturated output power of 23.3 dBm at 2.45 GHz. A maximum third-order output intercept point of 34 dBm is achieved at 20.2 dBm output power with a corresponding IMD3 of −33.4 dBc. When tested with a 20 MHz LTE signal, the PA delivers 19 dBm maximum linear output power for an adjacent channel leakage ratio specification of −30 dBc.Originality/valueIn this study, a novel cascaded gm3 cancellation technique has been implemented to achieve a maximum linear output power under modulated signals.

Design and implementation of low power and high speed multiplier using quaternary carry look-ahead adder

Need of Digital Signal Processing (DSP) systems which is embedded and portable has been increasing as a result of the speed growth of semiconductor technology. Multiplier is a most crucial part in almost every DSP application. So, the low power, high speed multipliers is needed for high speed DSP. Array multiplier is one of the fast multiplier because it has regular structure and it can be designed very easily. Array multiplier is used for multiplication of unsigned numbers by using full adders and half adders. It depends on the previous computations of partial sum to produce the final output. Hence, delay is more to produce the output. In the previous work, Complementary Metal Oxide Semiconductor (CMOS) Carry Look-ahead Adders (CLA) and CMOS power gating based CLA are used for maximizing the speed of the multiplier and to improve the power dissipation with minimum delay. CMOS logic is based on radix 2(binary) number system. In arithmetic operation, major issue corresponds to carry in binary number system. Higher radix number system like Quaternary Signed Digit (QSD) can be used for performing arithmetic operations without carry. The proposed system designed an array multiplier with Quaternary Signed Digit number system (QSD) based Carry Look-Ahead Adder (CLA) to improve the performance. Generally, the quaternary devices require simpler circuit to process same amount of data than that needed in binary logic devices. Hence the Quaternary logic is applied in the CLA to improve the speed of adder and high throughput. In array multiplier architecture, instead of full adders, carry look-ahead adder based on QSD are used. This facilitates low consumption of power and quick multiplication. Tanner EDA tool is used for simulating the proposed multiplier circuit in 180 nm technology. With respect to area, Power Delay Product (PDP), Average power proposed QSD CLA multiplier is compared with Power gating CLA and CLA multiplier.

Antiphase Method of the CMOS Power Amplifier Using PMOS Driver Stage to Enhance Linearity

We present the possibility of a complementary metal-oxide semiconductor (CMOS) power amplifier (PA) using a driver stage composed of p-channel metal oxide semiconductor (PMOS) to enhance linearity. The PMOS driver stage is designed as a cascode structure to adapt the antiphase technique to the CMOS PA. By biasing the common-source transistor of the driver stage at the subthreshold region, we obtain a gm3 value with a positive sign to cancel out the negative gm3 of the power stage, thereby enhancing the linearity. We also investigate the effect of the bias of the cascode transistor of the driver stage on third-order intermodulation distortion and amplitude-to-phase distortion. Consequently, we show that the PMOS driver stage itself acts as a pre-distorter of the power stage. To verify the possibility of the PMOS driver stage and the proposed biasing method for the antiphase technique, we design a 2.42 GHz PA using a 180 nm RFCMOS process for wireless local area network applications. We obtain a measured maximum linear output power of 21.5 dBm with a 23.4% power-added efficiency and an error vector magnitude of 3.14%. We use an 802.11 n modulated signal with 64-quadrature amplitude modulation (QAM) (MCS7) at 65 Mb/s.

1 mm3-sized optical neural stimulator based on CMOS integrated photovoltaic power receiver

In this work, we present a simple complementary metal-oxide semiconductor (CMOS)-controlled photovoltaic power-transfer platform that is suitable for very small (less than or equal to 1–2 mm) electronic devices such as implantable health-care devices or distributed nodes for the Internet of Things. We designed a 1.25 mm × 1.25 mm CMOS power receiver chip that contains integrated photovoltaic cells. We characterized the CMOS-integrated power receiver and successfully demonstrated blue light-emitting diode (LED) operation powered by infrared light. Then, we integrated the CMOS chip and a few off-chip components into a 1-mm3 implantable optogenetic stimulator, and demonstrated the operation of the device.

Fully integrated CMOS power amplifier using resistive current combining technique

This study presents a fully integrated complementary metal oxide semiconductor (CMOS) power amplifier (PA) covering LTE-advanced bands from 825 to 915 MHz for cellular application and the bands of 978 MHz universal access transceiver mode and 1090 MHz extended squitter mode of an automatic dependent surveillance-broadcast transmitter for the unmanned aircraft system. The 3.63 mm × 0.95 mm PA including all on-chip input and output matching networks, fabricated using the 0.18 μm CMOS process exhibits peak output power of 24 dBm, modulated output power of >22 dBm at 978 MHz, the maximum power gain of 27 dB and bandwidth of 290 MHz.

Design of Efficient Reversible BCD Adder–Subtractor Architecture and Its Optimization Using Carry Skip Logic

In the present era, reversible logic designs play a very critical role in nanotechnology, low power complementary metal-oxide semiconductor (CMOS) designs, optical computing and, especially, in quantum computing. High power dissipation and leakage current in deep submicron technologies is a severe threat in applications created today. As a consequence, design of datapath elements in reversible logic has gained much importance. In this study, a novel design of binary coded decimal (BCD) adder/subtractor in reversible logic has been proposed. As a further optimization of the proposed reversible decimal design, carry skip (CSK) logic is used for reversible ripple carry adder stages. This reduces delay but at the expense of little hardware. The proposed BCD adder/subtractor and its optimized version are designed using structural VHDL and simulated using ModelSim 6.3f. Performance analysis reveals that the proposed BCD design demonstrates reductions in gate count, garbage outputs and constant inputs of 30.5%, 46% and 28%, respectively, and its optimized version exhibits 19.4%, 32.4% and 16% reductions in gate count, garbage outputs and constant inputs compared to the design in Ref. 14 [V. Rajmohan, V. Renganathan and M. Rajmohan, A novel reversible design of unified single digit BCD adder–subtractor, Int. J. Comput. Theor. Eng. 3 (2011) 697–700].

A Low Power High Gain CMOS LNA with Multiple-Feedback Network for Low Voltage UWB Receiver

In this paper, a high gain low voltage low power Complementary Metal Oxide Semiconductor (CMOS) Low-noise Amplifier (LNA) using Chartered 0.18[Formula: see text][Formula: see text]m CMOS process for Ultra-wideband (UWB) receiver applications is presented. A novel multiple-feedback network constructed by the shunt feedback resistor with a transformer is adopted to realize desirable bandwidth extension and less chip area occupation in the common-source stage. All the cascaded transistors are configured by current-reuse structure and adjusted by forward body bias technique to further reduce supply voltage and power dissipation. The post-layout simulation results demonstrate that the proposed 3.4–10.1[Formula: see text]GHz UWB LNA accomplishes a maximum gain of 14.26[Formula: see text]dB with only 2.33[Formula: see text]mW power consumption at 0.8[Formula: see text]V supply voltage, while Noise Figure (NF) is 1.49–3.41[Formula: see text]dB and the chip area is 0.46[Formula: see text]mm2 including test pads (core area is 0.23[Formula: see text]mm2).

Compact high‐linearity, high‐efficiency complementary metal–oxide–semiconductor power amplifier with post‐distortion lineariser for wireless local area network and Wireless Gigabit Alliance applications

This study proposes a post-distortion linearisation technique for 5 and 60 GHz complementary metal-oxide-semiconductor (CMOS) power amplifiers (PAs). The technique improves the output 1 dB gain compression point (OP 1dB ) and power-added efficiency (PAE) of the PA when the lineariser is turned on. The 5 GHz PA that is fabricated in tsmc TM 0.18 μm CMOS achieves a 16.3 dB gain, a 20 dBm OP 1dB and a 32.6% PAE. The linearised 5 GHz PA improves the OP 1dB and PAE by 2.3 dB and 3.2% as compared to the PA without lineariser. The difference between the OP 1dB and saturated power ( P sat ) is <;0.2 dB. The 60 GHz PA was implemented in a 90 nm CMOS process with a chip area of 0.57 mm 2 . The PA achieves a 14.8 dB gain, a 16.8 dBm OP 1dB with a 16.3% PAE and a 15 GHz 3 dB bandwidth. The power difference between the OP 1dB and P sat is <;0.3 dB. The linearised 60 GHz PA improves the OP 1dB and PAE by 3.2 dB and 5.8% as compared to the PA without lineariser.

A millimeter-wave CMOS power amplifier design using high-Q slow-wave transmission lines

A three-stage 60-GHz power amplifier (PA) has been implemented in a 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. High-quality-factor slow-wave coplanar waveguides (S-CPW) were used for input, output and inter-stage matching networks to improve the performance. Being biased for Class-A operation, the PA exhibits a measured power gain G of 18.3 dB at the working frequency, with a 3-dB bandwidth of 8.5 GHz. The measured 1-dB output compression point (OCP1dB) and the maximum saturated output power Psat are 12 dBm and 14.2 dBm, respectively, with a DC power consumption of 156 mW under 1.2 V voltage supply. The measured peak power added efficiency PAE is 16%. The die area is 0.52 mm2 (875 × 600 μm2) including all the pads, whereas the effective area is only 0.24 mm2. In addition, the performance improvement of the PA in terms of G, OCP1dB, Psat, PAE and the figure of merit using S-CPW instead of thin film microstrip have been demonstrated. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2015.

Low power complementary metal‐oxide semiconductor class‐G audio amplifier with gradual power supply switching

The architecture, design and implementation of a low power complementary metal-oxide semiconductor (CMOS) class-G audio amplifier with gradual power-supply switching (GPSS) are presented. The proposed class-G amplifier output stage strategically uses the parallel connection of a class-AB output stage operating from smaller supplies (V DDL/V SSL), and a class-C output stage (with crossover from V SSL to V DDL) operating from higher supplies (V DDH/V SSH). GPSS is achieved using an efficient biasing scheme with level shifters. Moreover, the proposed biasing scheme in conjunction with negative feedback enables low distortion during the power-supply transition. Experimentally, the class-G amplifier prototype achieves a −82.5 dB THD + N, a peak load power of 50 mW and a quiescent power consumption of 350 μW. The proposed class-G amplifier was implemented in a standard CMOS 90 nm technology and occupies an active silicon area of 0.08 mm2.