Abstract
A three-stage 60-GHz power amplifier (PA) has been implemented in a 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. High-quality-factor slow-wave coplanar waveguides (S-CPW) were used for input, output and inter-stage matching networks to improve the performance. Being biased for Class-A operation, the PA exhibits a measured power gain G of 18.3 dB at the working frequency, with a 3-dB bandwidth of 8.5 GHz. The measured 1-dB output compression point (OCP1dB) and the maximum saturated output power Psat are 12 dBm and 14.2 dBm, respectively, with a DC power consumption of 156 mW under 1.2 V voltage supply. The measured peak power added efficiency PAE is 16%. The die area is 0.52 mm2 (875 × 600 μm2) including all the pads, whereas the effective area is only 0.24 mm2. In addition, the performance improvement of the PA in terms of G, OCP1dB, Psat, PAE and the figure of merit using S-CPW instead of thin film microstrip have been demonstrated. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2015.
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