Abstract
This paper presents the design of an efficient two-stage m illim eter-wave power amplifier (PA) using stacked field-effect transistors in 45nm silicon-on-insulator (SOI) CMOS technology. It highlights two major issues encountered when designing single-ended multistage PAs at millimeter frequencies (e.g., 60GHz), namely the significant source to ground parasitic inductance and the vulnerability to oscillation at low frequencies. The two-stage differential PA includes input, inter-stage and output matching networks implemented using RF transformers with a high coupling factor and reduced insertion losses. The PA demonstrator showed a 3-dB bandwidth equal to 12GHz (55–67GHz). The small signal gain, peak power added efficiency and peak output power were recorded as 14.5dB, 25% and 17.3dBm, respectively.
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