Complementary Metal Oxide Semiconductor Inverter Research Articles

Flexible Complementary Metal‐Oxide‐Semiconductor Inverter Based on 2D p‐type WSe2 and n‐type MoS2

Transition metal dichalcogenides (TMDCs) are a promising class of two‐dimensional (2D) materials for flexible electronic applications due to their low integration temperature, good electronic properties, and excellent mechanical flexibility. Moreover, TMDCs offer the possibility of co‐integrating both n‐ and p‐type transistors on the same substrate, enabling the realization of complementary metal‐oxide‐semiconductor (CMOS) circuits. In this study, n‐type MoS2 field‐effect transistors (FETs), and p‐type WSe2‐FETs integrated on a flexible foil substrate fabricated by standard thin‐film technology are presented. These devices exhibit high stability in their electronic operation under strain and repeated bending cycles. A CMOS inverter based on these transistors is also successfully demonstrated, which shows excellent switching behaviour with high gain (up to 100), high noise margin (0.87 · VDD), and low average static power consumption (40 pW).

Area and Device Count Efficient Binary Logic Circuits using Anti‐Ambipolar Switch Devices

AbstractThe unique characteristics of an anti‐ambipolar switch (AAS) device exhibit Λ‐shaped transfer responses (namely delta conductance) and present unique opportunities to overcome the limit of silicon‐based, complementary metal‐oxide‐semiconductor (CMOS) logic circuits. It is crucial because a device that only turns on under a certain bias range can be utilized to simplify the logic circuit and reduce the device count and circuit area required to perform logic functions. In this study, a physically scalable AAS device is investigated using ZnO and dinaphtho[2,3‐b:2′,3′‐f]thieno[3,2‐b]thiophene as heterojunction structures to reduce the operating voltage and enhance the peak current and peak‐to‐valley ratio of the AAS device. Moreover, novel logic circuits for AND, OR, XOR, DEMUX, and half‐adder functions are demonstrated using AAS devices. AAS device‐based logic circuits exhibit power‐efficiency characteristics (≈49 times lower than that of the 90‐nm silicon‐based CMOS inverter) and reduce the transistor count and the circuit area by ≈67% and ≈70%, respectively. These results indicate that the use of AAS device‐based logic circuits can be a promising approach to overcome the physical scaling limit of current CMOS technology.

Third generation semiconductor device research: Optimizing CMOS and HEMT designs

The third-generation semiconductor device known as High Electron Mobility Transistors (HEMT) has found extensive applications in high-frequency and high-speed electronic systems. Its widespread usage in critical technologies such as radio telescopes, satellite broadcast receivers, and cellular base stations has established HEMT as a foundational technology underpinning our information and communication society. This paper provides an in-depth exploration of these semiconductor advancements. Firstly, the paper utilizes the CMOS inverter as a representative example to elucidate the fundamental structure of Complementary Metal-Oxide-Semiconductor (CMOS) technology. Additionally, it employs Gallium Arsenide (GaAs) HEMT as an illustrative instance to expound upon the architecture of HEMT devices. Furthermore, the paper delves into the optimization of CMOS technology, focusing on topics such as Multi-Threshold CMOS and the impact of the Width/Length (W/L) ratio. These discussions shed light on ways to enhance the performance of CMOS-based components. Additionally, the paper explores strategies to optimize HEMT devices, including the introduction of carbon doping and the application of the Grey-Wolf optimization technique. These approaches are critical in achieving higher efficiency and performance in HEMT-based applications.

A Study of High-Speed Hamming Distance Detection Circuit Utilizing a Neuron CMOS Inverter

This study tackles the challenge of optimizing associative memory for efficient data retrieval from large databases, crucial in real-time processing. The authors specifically address the issue of increased detection time in the minimum Hamming distance search associative memory, particularly as the number of data bits grows. This memory system utilizes Hamming distance as a key metric to identify the most similar reference data. Our contribution is the development of a new Hamming distance detection circuit employing neuron Complementary Metal Oxide Semiconductor (CMOS) inverters. This proposed circuit significantly outperforms existing models in terms of operational speed. The effectiveness and improved performance of the circuit are validated through simulations using HSPICE, a type of Simulation Program with Integrated Circuit Emphasis (SPICE) demonstrating its potential for more efficient real-time data retrieval applications.

Investigation on Germanium Transistors with HfOx-Based Gate Stacks for CMOS Operations

Germanium (Ge) FinFETs with HfOx-based gate stacks are fabricated to study the CMOS applications. To evaluate the logic circuit operation, the associated CMOS inverters are characterized. Compared to the HfO2, the Hf0.5Zr0.5Ox (HZO) gate stack provides higher drive currents and more symmetric Vth behaviors, which should be associated with the polarization effect. Through cyclic voltage transfer characteristic (VTC) operation and systematical analysis, it is found that both polarization and charge trapping in the gate stack impact the device characteristics. The HZO devices show a negative VTC shift with cycling, while the HfO2 devices reveal a positive shift. This opposite VTC behavior for both gate stack schemes indicates that the interaction of interface states and dipoles significantly influences the device operation. The results revealed in this work present a comprehensive understanding of HfOx-based device optimization.

Matched printed carbon nanotube complementary metal-oxide-semiconductor (CMOS) devices for flexible circuits

The development of matched carbon nanotube (CNT) complementary metal-oxide-semiconductor (CMOS) devices still remains a challenge for flexible and low-power-dissipation circuits. In this study, we found a reliable technique to achieve matched CNT CMOS thin-film transistors (TFTs) for integrated circuits (IC) with low power consumption. The enhancement-mode p-type CNT TFTs were obtained using the low-work-function Al gate electrodes and ultrathin (10 nm) Al2O3 dielectrics, which exhibit the average field-effect mobility(μ) of 6.5 cm2V−1s−1, subthreshold swing (SS) down to 70–85 mV/dec and on/off ratio up to 106 at the low working voltages between −1.5 V and 0.5 V, as well the outstanding stability and mechanical flexibility after 10,000 cycles of bending. Then, by adjusting the aspect ratios of the TFT channels and selectively dropping the electron-doping inks into p-type CNT TFTs’ channels, matched n-type and p-type CNT TFTs were obtained. Finally, flexible printed CMOS inverters with high noise tolerance (84% of 1/2 VDD), high voltage gain (over 32), and low power consumption (down to 32.9 pW) were successfully constructed, owing to the work style of CMOS circuits and electrically symmetrical n-type and p-type TFTs. Furthermore, good-performance NAND and NOR gates have been demonstrated. This work can effectively resolve the leakage current issue of flexible carbon-based electronics with the ultra-thin dielectrics by optimizing the conductive ink formula and printing technology.

Large-Scale Complementary Logic Circuit Enabled by Al2O3 Passivation-Induced Carrier Polarity Modulation in Tungsten Diselenide.

Achieving effective polarity control of n- and p-type transistors based on two-dimensional (2D) materials is a critical challenge in the process of integrating transition metal dichalcogenides (TMDC) into complementary metal-oxide semiconductor (CMOS) logic circuits. Herein, we utilized a proficient and nondestructive method of electron-charge transfer to achieve a complete carrier polarity conversion from p-to n-type by depositing a thin layer of aluminum oxide (Al2O3) onto tungsten diselenide (WSe2). By utilizing the Al2O3 passivation layer, we observed precisely tuned n-type behavior in contrast to transistors fabricated on the as-grown WSe2 film without any passivation layer, which display prominent p-type behavior. The polarity-transformed n-type WSe2 transistor from the pristine p-type shows the maximum ON current of ∼0.1 μA accompanied by a high electron mobility of 7 cm2 V-1 s-1 at a drain voltage (VDS) of 1 V. We successfully showcased a homogeneous CMOS inverter utilizing 2D-TMDC which exhibits an impressive voltage gain of 7 at VDD = 5 V. Moreover, this effective polarity control approach was further expanded upon to successfully demonstrate a range of logic circuits such as AND, OR, NAND, NOR logic gates, and SRAM. The proposed methodology possesses significant promise for facilitating the advancement of high-density circuitry components utilizing 2D-TMDC.

Fabrication and Characterization of Self-Aligned WSe2 p-Type Field-Effect Transistor

Semiconducting transition metal dichalcogenides (TMDCs) have been growing interests as channel materials in field effect transistors (FET) for next generation low power digital electronics. [1]. Since a complementary metal oxide-semiconductor (CMOS) inverter constructed from pairs of n-type and p-type FETs is a fundamental building blocks in modern digital electronics [2], implementation of both n-type and p-type FETs with semiconducting TMDCs is of particular importance [3]. Among various semiconducting TMDCs, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [4]. These prominent features of WSe2 is suitable for an application to CMOS inverter.One of the significant challenges is to develop a top gate and top contact FET structure with WSe2 for CMOS device integration on the same wafer. In addition, it is desirable to minimize the access region between channel and S/D contact because this access region served as a series resistance to channel resistance, resulting in the lower drain current in FET. This study reports a self-aligned process to fabricate top gate and top contact WSe2 p-type FET. In this self-aligned structure, the gate electrode and source/drain contact edges are automatically positioned and hence there are no overlap or access region between the gate and source/drain. The feature of this proposed method is that the gate stacks was utilized as a mask for self-aligned formation of WOx, which is source/drain contact for efficient hole injection [5]. The focus on this study is the impact of self-aligned structure of p-type WSe2 FET on the electrical characteristics. The effectiveness of proposed process was experimentally demonstrated by the fabrication and characterization of device.Figures 1 shows the self-aligned fabrication process of p-type WSe2 FET. 20 nm-thick SiO2 was formed by dry oxidation of p+-Si substrate. The mechanically exfoliated multi-layer WSe2 was transferred by PDMS stamp. Next, 15 nm-thick Al2O3 was prepared by ALD at 200 oC with H2O. Then, Nickel (Ni) metal was deposited by RF sputtering on Al2O3. Ni metal was patterned for gate electrode with conventional lithography process. After that, A2O3 layer was removed by wet etching. Subsequently, substrate was exposed to oxygen radicals to form WOx used as source/drain contact at surface of WSe2. Second layer of Al2O3 was deposited as an encapsulating passivation layer. After the contact hole opening, the electrical contact pad was fabricated. Finally, forming gas (N2 : H2 = 97 % : 3 %) annealing was performed at 200 oC for 30 min. The top gate length was 5 μm. The gate width was estimated to be 40 μm by optical microscope. The electrical characteristics were measured with a manual probe station in an atmospheric pressure without inert gas purge at room temperature using a precision semiconductor parameter analyzer (Agilent 4156 C).Figures 2 shows the Id–Vg characteristics of fabricated FETs for (a) back gate operation and (b) top gate operation. Representative Id–Vg characteristics of p-type FETs were observed irrespective of back gate and top gate operation. The on/off ratio of about 106 ~ 107 order were obtained for both back gate and top gate operation. Furthermore, the threshold voltage and sub-threshold slope were modulated by varying the substrate bias during gate sweep.This study opens up interesting directions for the research and development of TMDC-based devices.AcknowledgmentsThis study was supported by a JSPS Grant-in-Aid for Scientific Research (C) (Grant No. 20K04616), a research grant for Tokyo Tech Challenging Research Award, the Samco Foundation and a research grant for Suematsu Award.

Large‐Scale N‐Type FET and Homogeneous CMOS Inverter Array Based on Few‐Layer MoTe2

Abstract2D MoTe2 is regarded as a favorable candidate for semiconductor nanoelectronics integration. Chemical‐vapor‐deposition‐grown MoTe2 usually presents p‐type characteristics. In order to realize basic electronic units like complementary metal‐oxide‐semiconductor (CMOS) inverter, controllable fabrication of p‐ and n‐type transistors at large scale is of vital importance. Here, large‐scale MoTe2 n‐channel field‐effect transistor (n‐FET) arrays are successfully fabricated with seamless coplanar metallic 1T′‐WTe2 contacts to reduce contact resistance. High‐k HfO2 serves as a gate dielectric and its atomic‐layer‐deposition (ALD) process causes an n‐doping effect on the 2H‐MoTe2 channel. The FETs perform typical n‐type characteristics with average electron density and on/off ratio of ≈1.7 × 1013 cm−2 and 2.1 × 104, respectively. Furthermore, large‐scale homogeneous CMOS inverter arrays are fabricated, showing clear logic swing with low power consumption (≈0.4 nW) and high device yield (≈92%). Notably, their voltage transfer characteristics exhibit small hysteresis, and they work well after being kept in air for 16 months, indicating high device stability. The statistical results show that both the n‐FETs and CMOS inverters have high uniformity and reliability in performance. Significantly, this fabrication method is free from transfer processes and compatible with traditional silicon technology. This work paves the way for the application of few‐layer MoTe2 in semiconductor nanoelectronics integration.

Energy-Efficient circuits with improved diode free adiabatic logic design methodology

This paper demonstrates a detailed analysis of an unique improved diode-free adiabatic logic (IDFAL) circuit. The IDFAL is operated based on adiabatic switching principle. To indicate the circuit effectiveness, numerous analyses are carried out on different complementary metal oxide semiconductor (CMOS) technology nodes. Logic circuits, viz., NOT and NAND are analyzed and simulated using the traditional CMOS design style and some popular adiabatic logic design techniques: two-phase clocked adiabatic static CMOS logic (2PASCL), diode free adiabatic logic (DFAL), adiabatic dynamic CMOS logic (ADCL), two-phase adiabatic dynamic CMOS logic (2PADCL), quasi-static energy recovery logic (QSERL), and clocked CMOS adiabatic logic (CCAL). The results are compared with the proposed design (IDFAL) at various operating frequencies. The results revealed that the IDFAL inverter circuit has the least power delay product (PDP) among the reported adiabatic design methodologies and saves 91.59 % over the counter-part CMOS inverter at 16 nm high-performance predictive technologies (HP_PTM).

Low Leakage CMOS Design Technique with Stable State Retention

In this research, a new hybrid design technique for low-power complementary metal–oxide semiconductor (CMOS) circuits is proposed which utilizes the advantages of multiple design methodologies such as sleep-transistors, forced-stack, and variable-threshold CMOS (VTCMOS), and is integrated with a buffer circuit. Based on the proposed technique, the CMOS inverter and two-input NAND circuits are simulated in LTspice software using 16 nm high-performance (HP) and low-power (LP) predictive technology models (PTM). Upon comparison with available leakage reduction techniques, the proposed approach demonstrates considerably low power, delay and power delay product (PDP) while maintaining output-logic integrity. The impact of the process parameter, voltage, and temperature (PVT) variations are observed through Monte Carlo simulations, which depict that the proposed model provides uniform sensitivity in terms of the performance metrics within ±3σ statistical variations from the mean. The circuit area of the proposed technique is also estimated and compared with existing methods using the Cadence Virtuoso platform.

High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET.

This research presents the optimization and proposal of P- and N-type 3-stacked Si0.8Ge0.2/Si strained super-lattice FinFETs (SL FinFET) using Low-Pressure Chemical Vapor Deposition (LPCVD) epitaxy. Three device structures, Si FinFET, Si0.8Ge0.2 FinFET, and Si0.8Ge0.2/Si SL FinFET, were comprehensively compared with HfO2 = 4 nm/TiN = 80 nm. The strained effect was analyzed using Raman spectrum and X-ray diffraction reciprocal space mapping (RSM). The results show that Si0.8Ge0.2/Si SL FinFET exhibited the lowest average subthreshold slope (SSavg) of 88 mV/dec, the highest maximum transconductance (Gm, max) of 375.2 μS/μm, and the highest ON-OFF current ratio (ION/IOFF), approximately 106 at VOV = 0.5 V due to the strained effect. Furthermore, with the super-lattice FinFETs as complementary metal-oxide-semiconductor (CMOS) inverters, a maximum gain of 91 v/v was achieved by varying the supply voltage from 0.6 V to 1.2 V. The simulation of a Si0.8Ge0.2/Si super-lattice FinFET with the state of the art was also investigated. The proposed Si0.8Ge0.2/Si strained SL FinFET is fully compatible with the CMOS technology platform, showing promising flexibility for extending CMOS scaling.

180 nm FLASH ANALOG TO DIGITAL CONVERTOR

In this paper, Threshold Inverter Quantizer (TIQ) is a novel idea which can effectively replace the reference voltage generator, resistive/capacitive voltage divider network and array of differential comparators in a conventional flash Analog to Digital Converter (ADC) by an internal reference comparator array constructed of Complementary Metal Oxide Semiconductor (CMOS) inverters. The inverter threshold voltage serving as the reference voltage, this architecture claims large improvements in terms of silicon area, power consumption and operating speed. Perturbations due to sensitivity of the inverter threshold voltage to operating temperature/process variations pose impediments in such ADC designs and strongly demand a compensation scheme to such variations. This paper presents a TIQ based flash ADC, with inverter threshold voltage compensation. In this project 5 bit flash adc using TIQ Comparator is designed and simulated using TANNER EDA in 180nm technology. Key Words: flash, adc, tiq(threshold inverter quantization)

The Significance of an In Situ ALD Al2O3 Stacked Structure for p‐Type SnO TFT Performance and Monolithic All‐ALD‐Channel CMOS Inverter Applications

AbstractTin monoxide (SnO) has been studied widely over the past several decades due to its promising theoretical p‐type performance. However, limited fabrication processes due to the low thermal and air stability of SnO have resulted in poor performance in thin‐film transistors (TFTs). Here, it is suggested that in situ atomic layer deposition (ALD) of an Al2O3 capping layer can improve the electrical performance in SnO TFTs. By adopting an in situ stacking process, which protects vulnerable SnO thin films from exposure to air and contamination, SnO exhibits enhanced crystallinity, electrical performance, and improved scaling limitation of channel thickness. Especially, in situ stacked Al2O3 on a 7 nm SnO TFT has an exceptionally low subthreshold swing (0.15 V decade−1), high on/off ratio (6.54 × 105), and reasonable mobility (1.14 cm2 V−1 s−1) while the bare SnO TFT is not activated. Computational thermodynamics such as chemical potential analysis, nucleation Gibbs free‐energy calculations, and various analytical techniques are used to reveal the origin of highly crystallized SnO formations via in situ deposition of Al2O3. Finally, state‐of‐the‐art all‐ALD‐channel complementary metal–oxide–semiconductor inverters using n‐type indium gallium zinc oxide and p‐type SnO TFTs are integrated, which exhibit a maximum voltage gain of 240 V V−1 and a noise margin of 89.3%.

High-Performance CMOS Inverter Array with Monolithic 3D Architecture Based on CVD-Grown n-MoS2 and p-MoTe2.

In thiswork, monolithic three-dimensional complementary metal oxide semiconductor (CMOS) inverter array has been fabricated, based on large-scale n-MoS2 and p-MoTe2 grown by the chemical vapor deposition method. In the CMOS device, the n- and p-channel field-effect transistors (FETs) stack vertically and share the same gate electrode. High k HfO2 is used as the gate dielectric. An Al2 O3 seed layer is used to protect the MoS2 from heavily n-doping in the later-on atomic layer deposition process. P-MoTe2 FET is intentionally designed as the upper layer. Because p-doping of MoTe2 results from oxygen and water in the air, this design can guarantee a higher hole density of MoTe2 . An HfO2 capping layer is employed to further balance the transfer curves of n- and p-channel FETs and improve the performance of the inverter. The typical gain and power consumption of the CMOS devices are about 4.2 and 0.11 nW, respectively, at VDD of 1V. The statistical results show that the CMOS array is with high device yield (60%) and an average voltage gain value of about 3.6 at VDD of 1 V. This work demonstrates the advantage of two-dimensional semi-conductive transition metal dichalcogenides in fabricating high-density integrated circuits.

Dual-Channel WS2/WSe2 Heterostructure with Tunable Graphene Electrodes

Two-dimensional semiconductor heterostructures provide significant research potential for electronic and optoelectronic applications because of their scaled thickness, pristine heterostructure interface, and ultrafast carrier transport. Herein, we report a dual-channel field-effect transistor based on n-type WS2 and p-type WSe2 layered heterostructure using multilayered graphene as electrodes to enable electron-dominated ambipolar electrical transport. WS2 exhibits mobility of 20 cm2 V–1 s–1 and an on/off ratio of 105, whereas WSe2 exhibits mobility of 5 cm2 V–1 s–1 and an on/off ratio of 104. Furthermore, our results show negative Schottky barrier heights between dual-channel heterostructure and multilayered graphene. The proposed design reduces complications in the fabrication of devices with integrated heterostructures, particularly for complementary metal-oxide semiconductor inverter applications.

Doping-Free Complementary Metal-Oxide-Semiconductor Inverter Based on N-Type and P-Type Tungsten Diselenide Field-Effect Transistors With Aluminum-Scandium Alloy and Tungsten Oxide for Source/Drain Contact

In this study, we experimentally demonstrated concepts for realizing doping-free Tungsten Diselenide (WSe2) complementary metal-oxide-semiconductor (CMOS) inverter by developing alloys and compound metals used as source/drain (S/D) contacts. Aluminum – scandium alloy (AlSc) and tungsten oxide (WOx)-based S/D contacts enable efficient electron and hole injection into WSe2 for n-type and p-type FET operation because the work function (WF) of AlSc and WOx are aligned to neighboring the conduction and valence band edge of WSe2, respectively. A dual-gate bias architecture is used to improve electrical characteristics of FETs and enhance CMOS inverter performance after device fabrication. By utilizing AlSc and WOx-based S/D contacts in conjunction with the dual-gate bias architecture, our fabricated WSe2 CMOS inverter realized a higher gain at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ dd}}$ </tex-math></inline-formula> of 1 V or higher than those in the literatures. Furthermore, the fabricated WSe2 CMOS inverter is operated at a power supply voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ dd}}$ </tex-math></inline-formula> ) of as low as 0.5 V. This study paves the way towards research and development of transition metal dichalcogenides-based devices and circuits.

Design and Optimization of Ultradeep Submicron CMOS Inverter Using a Unified All Regional MOSFET Model

Complementary Metal Oxide Semiconductor (CMOS) has always remained the dominant integrated circuit technology specifically for designing digital circuits. This paper examines the modelling (utilizing $\alpha$-power based MOSFET model), simulation (utilizing HSPICE simulation) and optimization (utilizing Particle Swarm Optimization (PSO) and Artificial Bee Colony (ABC) techniques) of ultradeep submicron CMOS based digital inverter, performs insightful analysis and extracts formulas for the optimal transistor sizing. Additionally, the study serves as an implementation forum for the thermal analysis of transient characteristics of CMOS inverters at the ultradeep submicron technology node (at 300K and 400K). The results lie within the acceptable range of 1-10\%.

Elucidation of electric characteristics for P and N type polycrystalline silicon vertical thin film transistors

P and N type polycrystalline silicon has been applied in thin film transistors (TFTs) for driving a range of displays, and for building up complementary metal oxide semiconductor (CMOS)-like circuits. In one aspect, the high driving current is required, which is usually achieved by improving field effect mobility of the active layer. For another, balanced electrical characteristics are required for achieving CMOS-like logic circuits. In this article, in order to increase driving current, P and N type polycrystalline silicon vertical TFTs configuration is proposed that can get rid of the strict requirement of the field effect mobility in order to increase the driving current. In addition, the balanced electrical properties are demonstrated for P and N type vertical TFTs, which are elucidated by the density of states calculations. The simple Simulation Program with Integrated Circuit Emphasis (SPICE) modelling indicates the potential application in CMOS inverter based on our vertical TFTs.

(Invited, Digital Presentation) Low Voltage Operation of CMOS Inverter Based on WSe2 n/p FETs

Transition metal dichalcogenides (TMDC) have remarkable properties for the next generation of electronic devices [1]. A complementary metal-oxide-semiconductor (CMOS) inverter consisting of pairs of p-type and n-type field-effect transistor (FET) is a fundamental building block in modern digital electronics [2]. Therefore, realization of both p-type and n-type FETs based on semiconducting TMDC is of particular importance. Among various semiconducting TMDC, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [3]. These prominent features of WSe2 motivates the fabrication and characterization of a CMOS inverter. One of the significant challenges is to develop a high-gain CMOS inverter for operation at a low power supply voltage (Vdd) for future low power digital electronics. Previous studies on a WSe2 CMOS inverter were limited to operation with a low gain of 3 or a high Vdd of more than 1 V under conditions of relatively low gate capacitance and degraded interfacial properties [3-5]. This study addressed these issues by developing a doping technique and gate stack technology to demonstrate the high-gain with low-Vdd operation of a WSe2 CMOS inverter [6]. The focus is on the doping technique of both electrons and holes to a WSe2 layer by simple spin-coating. Of particular interest in this study is the impact of gate stack technology on the CMOS inverter characteristics in low-Vdd operation. In this study, a hybrid self-assembled monolayer (SAM)/aluminum oxide (AlOx) gate dielectric is applied to a WSe2 CMOS inverter for high-gain low-Vdd operation since superior interfacial properties with high gate capacitance have been reported in molybdenum disulfide (MoS2) FETs.For p-type WSe2 FETs, the fluoropolymer CYTOP (AGC, CTX-809A) was applied since polarization in CYTOP due to the difference in electronegativity between C–F bonds generates holes in WSe2. On the other hand, poly(vinyl alcohol) (PVA) was utilized for n-type WSe2 FETs because positive charges in PVA accumulates electrons in WSe2. The resin solutions of both CYTOP and PVA were purchased from a commercial supplier. A heavily doped p-type silicon substrate (p+-Si) was thermally oxidized to form a 60 nm thick silicon dioxide (SiO2) layer for the global back-gate architecture. Palladium (Pd) and gold (Au) as the source and drain contacts for p-type and n-type WSe2 FETs were fabricated by the lift-off process, respectively. An aluminum (Al) gate was prepared and a hybrid SAM/AlOx gate dielectric was formed by oxygen (O2) plasma and an immersion process. After that, mechanically exfoliated WSe2 was transferred with a poly(dimethylsiloxane) (PDMS) stamp. Finally, CYTOP and PVA were deposited by spin-coating for p-type and n-type WSe2 FETs, respectively.Figures 1 (a) and (b) show the Id–Vg characteristics of fabricated FETs. For the p-type WSe2 FET, a small SS of 78 mV/dec and an on/off ratio of about 106 order were observed. On the other hand, the Id–Vg characteristics of the n-type WSe2 FET were degraded compared with those of the p-type WSe2 FET because of the Schottky contacts.Figures 2 (a) and (b) show the transfer characteristics and gain as a function of Vdd in CMOS inverter. The gain of the CMOS inverter increased to as high as 9 at Vdd of 0.5 V.Figure 3 shows the benchmark of this study. Our proposed concepts enabled the operation with high gain at a low Vdd as low as 0.5 V for the WSe2 CMOS inverter, which had not been realized in previous studies. The dangling-bond-free and ultrathin SAM/AlOx gate dielectric has an important role in the low-Vdd operation of the WSe2 CMOS inverter. This study opens up interesting directions for the research and development of TMDC-based devices and circuits.