Complementary Metal Oxide Semiconductor Inverter Research Articles

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

In this paper, a hybrid 1-bit full adder design employing both complementary metal–oxide–semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for 1 bit and then extended for 32 bit also. The circuit was implemented using Cadence Virtuoso tools in 180-and 90-nm technology. Performance parameters such as power, delay, and layout area were compared with the existing designs such as complementary pass-transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS output drive full adder, and so on. For 1.8-V supply at 180-nm technology, the average power consumption (4.1563 $\mu $ W) was found to be extremely low with moderately low delay (224 ps) resulting from the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. Corresponding values of the same were 1.17664 $\mu $ W and 91.3 ps at 90-nm technology operating at 1.2-V supply voltage. The design was further extended for implementing 32-bit full adder also, and was found to be working efficiently with only 5.578-ns (2.45-ns) delay and 112.79- $\mu $ W (53.36- $\mu $ W) power at 180-nm (90-nm) technology for 1.8-V (1.2-V) supply voltage. In comparison with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power and speed.

High-performance, mechanically flexible, and vertically integrated 3D carbon nanotube and InGaZnO complementary circuits with a temperature sensor.

A vertically integrated inorganic-based flexible complementary metal-oxide-semiconductor (CMOS) inverter with a temperature sensor with a high inverter gain of ≈50 and a low power consumption of <7 nW mm(-1) is demonstrated using a layer-by-layer assembly process. In addition, the negligible influence of the mechanical flexibility on the performance of the CMOS inverter and the temperature dependence of the CMOS inverter characteristics are discussed.

Selective p- and n-Doping of Colloidal PbSe Nanowires To Construct Electronic and Optoelectronic Devices.

We report the controlled and selective doping of colloidal PbSe nanowire arrays to define pn junctions for electronic and optoelectronic applications. The nanowires are remotely doped through their surface, p-type by exposure to oxygen and n-type by introducing a stoichiometric imbalance in favor of excess lead. By employing a patternable poly(methyl)methacrylate blocking layer, we define pn junctions in the nanowires along their length. We demonstrate integrated complementary metal-oxide semiconductor inverters in axially doped nanowires that have gains of 15 and a near full signal swing. We also show that these pn junction PbSe nanowire arrays form fast switching photodiodes with photocurrents that can be optimized in a gated-diode structure. Doping of the colloidal nanowires is compatible with device fabrication on flexible plastic substrates, promising a low-cost, solution-based route to high-performance nanowire devices.

Low temperature processed complementary metal oxide semiconductor (CMOS) device by oxidation effect from capping layer.

In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190°C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

A high-performance complementary inverter based on transition metal dichalcogenide field-effect transistors.

For several years, graphene has been the focus of much attention due to its peculiar characteristics, and it is now considered to be a representative 2-dimensional (2D) material. Even though many research groups have studied on the graphene, its intrinsic nature of a zero band-gap, limits its use in practical applications, particularly in logic circuits. Recently, transition metal dichalcogenides (TMDs), which are another type of 2D material, have drawn attention due to the advantage of having a sizable band-gap and a high mobility. Here, we report on the design of a complementary inverter, one of the most basic logic elements, which is based on a MoS2 n-type transistor and a WSe2 p-type transistor. The advantages provided by the complementary metal-oxide-semiconductor (CMOS) configuration and the high-performance TMD channels allow us to fabricate a TMD complementary inverter that has a high-gain of 13.7. This work demonstrates the operation of the MoS2 n-FET and WSe2 p-FET on the same substrate, and the electrical performance of the CMOS inverter, which is based on a different driving current, is also measured.

Modulating the morphology and electrical properties of GaAs nanowires via catalyst stabilization by oxygen.

Nowadays, III-V compound semiconductor nanowires (NWs) have attracted extensive research interest because of their high carrier mobility favorable for next-generation electronics. However, it is still a great challenge for the large-scale synthesis of III-V NWs with well-controlled and uniform morphology as well as reliable electrical properties, especially on the low-cost noncrystalline substrates for practical utilization. In this study, high-density GaAs NWs with lengths >10 μm and uniform diameter distribution (relative standard deviation σ ∼ 20%) have been successfully prepared by annealing the Au catalyst films (4-12 nm) in air right before GaAs NW growth, which is in distinct contrast to the ones of 2-3 μm length and widely distributed of σ ∼ 20-60% of the conventional NWs grown by the H2-annealed film. This air-annealing process is found to stabilize the Au nanoparticle seeds and to minimize Ostwald ripening during NW growth. Importantly, the obtained GaAs NWs exhibit uniform p-type conductivity when fabricated into NW-arrayed thin-film field-effect transistors (FETs). Moreover, they can be integrated with an n-type InP NW FET into effective complementary metal oxide semiconductor inverters, capable of working at low voltages of 0.5-1.5 V. All of these results explicitly demonstrate the promise of these NW morphology and electrical property controls through the catalyst engineering for next-generation electronics.

Complete delay modeling of sub‐threshold CMOS logic gates for low‐power application

SummaryIn this paper, the propagation delay of a complementary metal‐oxide semiconductor (CMOS) inverter circuit in sub‐threshold regime has been analyzed thoroughly with respect to variable loads, rise and fall time of input, device dimensions and temperature, without neglecting the significant drain induced barrier lowering (DIBL) and body bias effects. In particular, sub‐threshold slope factor and current strength have been modeled with respect to temperature, which would be efficacious for the analysis of sub‐threshold circuit as temperature plays an important role in propagation delay. Transistor stacking has also been modeled considering variation in threshold voltage, sub‐threshold slope factor and DIBL coefficient owing mainly to fluctuation in doping levels. The CMOS inverter delay model together with transistor stacking model has been incorporated in the analysis of propagation delays of NAND and NOR gates. Extensive simulations have been performed under 45 and 22 nm CMOS technology using simulation program with integrated circuit emphasis (SPICE) to ensure the correctness of the analysis. Simulation shows that this model is applicable for the analysis of digital sub‐threshold circuit in sub‐90 nm technology. Copyright © 2015 John Wiley &amp; Sons, Ltd.

Single event transients in a 0.18 m partially-depleted silicon-on-insulator complementary metal oxide semiconductor circuit

Single event transients (SETs) in a 100 series 0.18 m partially- depleted silicon-on-insulator (PDSOI) complementary metal oxide semiconductor (CMOS) inverter chain are studied by using pulsed laser. In this paper, effects of struck transistor type and struck locations on the threshold laser energy and the pulse width of SETs are investigated. Results show that the threshold laser energies at different locations are similar, but the threshold laser energies of n-channel metal-oxide-semiconductor (NMOS) transistors are much smaller than that of p-channel metal-oxide-semiconductor (PMOS) transistors. The SET pulse width of n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) is 427.5 ps as measured at the output terminal when the 2nd stage is irradiated, and 287.4 ps when the 100th stage is irradiated; the SET pulse width of p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) is 295.9 ps as measured at the output terminal when the 1st stage is irradiated, and 150.5 ps when the 99th stage is irradiated. Both broadening rates are about 1.4 ps/stage. When the struck locations are close to the output terminal of the chain, the SET pulse is narrowed; however, when the struck nodes are close to the input terminal, the SET pulse is broadened. SET pulses are progressively broadened up when propagating is along inverter chains. A similar broadening rate in neither NMOSFET nor PMOSFET, indicates that the SET pulse broadening effect is caused by propagation, independent of the type of struck transistors. Through analysis, the charge of floating body-induced threshold voltage hysteresis in PDSOI transistors is the main cause of pulse broadening. The positive SET pulse observed on the oscilloscope, contrary to the expectation, is due to charging and discharging of the output node capacitor. Also, the observed sub-rail-to-rail swings of the SET pulses are due to the voltage division between the internal resistance of the oscilloscope and the resistance of the PMOS transistor.

Complementary Oxide–Semiconductor-Based Circuits With n-Channel ZnO and p-Channel SnO Thin-Film Transistors

Fully oxide thin-film transistor (TFT)-based complementary metal-oxide-semiconductor (CMOS) ring oscillators are reported, for the first time, using large-area-compatible sputtering processes. The p-channel tin monoxide (SnO) and n-channel zinc oxide (ZnO) TFTs used in the CMOS inverter have inverted-staggered bottom-gate structures. The SnO TFT exhibits a threshold voltage (Vth) of 3.5 V, field-effect mobility of 0.33 cm 2 /V-s, subthreshold swing of 2.5 V/decade, and ON/OFF current ratio of ~10 3 . The corresponding values for the ZnO TFT are 6.22 V, 3.5 cm 2 /V-s, 350 mV/decade, and >10 6 . The achieved voltage gain of the CMOS inverters is ~17 at a supplied voltage (VDD) of 10 V when the geometric aspect ratio is 5. An oscillation frequency of 2 kHz is obtained from a five-stage oxide-based CMOS voltage control oscillator at (VDD) of 14 V.

Operation voltage reduction and gain enhancement in organic CMOS inverters with the TTC/gelatin bilayer dielectric

An air ambient operated organic complementary metal oxide semiconductor (CMOS) inverter has been fabricated on poly(ethylene terephthalate) (PET) using pentacene and N,N-dioctyl-3,4,9,10-perylene tetracarboxylic diimide (PTCDI-C8) as active layers with a bilayer dielectric of tetratetracontane (TTC) and gelatin. The inverter performance is greatly improved by replacing the gelatin dielectric with the TTC/gelatin bilayer. With the TTC/gelatin bilayer, both types of organic field-effect transistor (OFET) show better pinch-off and current saturation in output characteristics and negligible hysteresis transfer characteristics. The organic CMOS inverter with the TTC/gelatin bilayer dielectric exhibits balanced motilities of 0.5 (pentacene) and 0.3cm2V−1s−1 (PTCDI-C8) with low threshold voltages of −1 (pentacene) and 3V (PTCDI-C8). A high static gain of 60 may be achieved with sharp inversion.

A linearity-enhanced time-domain CMOS thermostat with process-variation calibration.

This study proposes a linearity-enhanced time-domain complementary metal-oxide semiconductor (CMOS) thermostat with process-variation calibration for improving the accuracy, expanding the operating temperature range, and reducing test costs. For sensing temperatures in the time domain, the large characteristic curve of a CMOS inverter markedly affects the accuracy, particularly when the operating temperature range is increased. To enhance the on-chip linearity, this study proposes a novel temperature-sensing cell comprising a simple buffer and a buffer with a thermal-compensation circuit to achieve a linearised delay. Thus, a linearity-enhanced oscillator consisting of these cells can generate an oscillation period with high linearity. To achieve one-point calibration support, an adjustable-gain time stretcher and calibration circuit were adopted for the process-variation calibration. The programmable temperature set point was determined using a reference clock and a second (identical) adjustable-gain time stretcher. A delay-time comparator with a built-in customised hysteresis circuit was used to perform a time comparison to obtain an appropriate response. Based on the proposed design, a thermostat with a small area of 0.067 mm2 was fabricated using a TSMC 0.35-μm 2P4M CMOS process, and a robust resolution of 0.05 °C and dissipation of 25 μW were achieved at a sample rate of 10 samples/s. An inaccuracy of −0.35 °C to 1.35 °C was achieved after one-point calibration at temperatures ranging from −40 °C to 120 °C. Compared with existing thermostats, the proposed thermostat substantially improves the circuit area, accuracy, operating temperature range, and test costs.

Fabrication of poly‐Si complementary metal oxide semiconductor inverter by all sputtering deposition process

AbstractDirect current sputtering was used for deposition of Si film for precursor film of excimer laser annealing, n+‐Si/p+‐Si film for source/drain contact, and SiO2 film for gate insulator of polycrystalline silicon thin‐film transistor. Using these methods, poly‐Si thin‐film complementary metal oxide semiconductor inverter was fabricated by all sputtering process for the first time. The field‐effect mobility was, respectively, 6.5 and 12.5 cm2/Vs for n‐TFTs and p‐TFTs. This inverter exhibits a full rail‐to‐rail swing and abrupt voltage transfer characteristics over the entire voltage range, and the output voltage gain was ~117 at Vdd = 20 V.

POWER GATING TECHNIQUE USING FinFET FOR MINIMIZATION OF SUB-THRESHOLD LEAKAGE CURRENT

In this paper, a novel power gating method has been proposed with the combination of complementary metal oxide semiconductor (CMOS) logic and FinFET for better sub-threshold leakage current minimization. Sub-threshold leakage currents take the paramount part in overall contribution to total power dissipation which comprises of scaling and power reduction. Power gating technique takes up priority among the different leakage current reduction mechanisms. The novel approach has been applied to a CMOS inverter and a two input CMOS NAND gate. The inverter simulated with high threshold voltage metal oxide semiconductor field effect transistor (MOSFET), VGOT MOSFET and fin field effect transistor (FinFET) as sleep transistor reduces the sub-threshold leakage current by 45.529%, 47.265% and 86.431%, respectively, when compared with inverter in absence of sleep transistor. This proves substantial improvement as compared to the planar CMOS inverter. Further, these techniques applied for a two input NAND gate resulted in reduction of leakage current by 20.536%, 23.955% and 99.942%, respectively.

Fabrication of Stretchable Single‐Walled Carbon Nanotube Logic Devices

The fabrication of a stretchable single-walled carbon nanotube (SWCNT) complementary metal oxide semiconductor (CMOS) inverter array and ring oscillators is reported. The SWCNT CMOS inverter exhibits static voltage transfer characteristics with a maximum gain of 8.9 at a supply voltage of 5 V. The fabricated devices show stable electrical performance under the maximum strain of 30% via forming wavy configurations. In addition, the 3-stage ring oscillator demonstrates a stable oscillator frequency of ∼3.5 kHz at a supply voltage of 10 V and the oscillating waveforms are maintained without any distortion under cycles of pre-strain and release. The strains applied to the device upon deformation are also analyzed by using the classical lamination theory, estimating the local strain of less than 0.6% in the SWCNT channel and Pd electrode regions which is small enough to keep the device performance stable under the pre-strain up to 30%. This work demonstrates the potential application of stretchable SWCNT logic circuit devices in future wearable electronics.

Molecular Packing‐Induced Transition between Ambipolar and Unipolar Behavior in Dithiophene‐4,9‐dione‐Containing Organic Semiconductors

By changing the packing motif of the conjugated cores and the thin‐film microstructures, unipolar organic semiconductors may be converted into ambipolar materials. A combined experimental and theoretical investigation is conducted on the thin‐film organic field‐effect transistors (OFETs) of three organic semiconductors that have the same conjugated core structure of s‐indaceno[1,2‐b:5,6‐b′]dithiophene‐4,9‐dione but with different n‐alkyl groups. The optical and electrochemical measurements suggest that the three organic semiconductors have very similar energy levels; however, their OFETs exhibit dramatically different transport characteristics. Transistors based on compound 1a or 1c show ambipolar transport properties, while those based on compound 1b show p‐type unipolar behavior. Specifically, compound 1c is characterized as a good ambipolar semiconductor with the highest electron mobility of 0.22 cm2 V−1 s−1 and the highest hole mobility of 0.03 cm2 V−1 s−1. Complementary metal oxide semiconductor (CMOS) inverters incorporated with compound 1c show sharp inversions with high gains above 50. Theoretical investigations reveal that the drastic difference in the transport properties of the three materials is due to the difference in their molecular packing and film microstructures.

High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.

We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire field-effect-transistors (NWFETs) via a low-temperature fabrication processing technique. We demonstrate that NWCMOS inverter devices can be operated at less than 1 V, a significantly lower voltage than that of typical thin-film based complementary metal-oxide semiconductor (CMOS) inverter devices. This low-voltage operation was accomplished by controlling the threshold voltage of the n-type Si NWFETs through effective management of the nanowire (NW) doping concentration, while realizing high voltage gain (>10) and ultra-low static power dissipation (≤3 pW) for high-performance digital inverter devices. This result offers a viable means of fabricating high-performance, low-operation voltage, and high-density digital logic circuits using a low-temperature fabrication processing technique suitable for next-generation flexible electronics.

Subnanowatt Carbon Nanotube Complementary Logic Enabled by Threshold Voltage Control

In this Letter, we demonstrate thin-film single-walled carbon nanotube (SWCNT) complementary metal-oxide-semiconductor (CMOS) logic devices with subnanowatt static power consumption and full rail-to-rail voltage transfer characteristics as is required for logic gate cascading. These results are enabled by a local metal gate structure that achieves enhancement-mode p-type and n-type SWCNT thin-film transistors (TFTs) with widely separated and symmetric threshold voltages. These complementary SWCNT TFTs are integrated to demonstrate CMOS inverter, NAND, and NOR logic gates at supply voltages as low as 0.8 V with ideal rail-to-rail operation, subnanowatt static power consumption, high gain, and excellent noise immunity. This work provides a direct pathway for solution processable, large area, power efficient SWCNT advanced logic circuits and systems.

ZrO2 dielectric-based low-voltage organic thin-film inverters

In this paper, the authors first report ZrO2-dielectric based low-voltage organic thin-film complementary metal-oxide semiconductor inverters. Two active layers of p-type pentacene and n-type N,N′-dioctyl-3,4,9,10-perylenedicarboximide were successively deposited on the thermally stable, transparent ZrO2 using the neutral cluster beam deposition method. Based on the good balance between p- and n-type transistors, the complementary inverters exhibited ideal characteristics including sharp inversions, complete switching, high gains, and large voltage swings at low operating voltage levels.

Tunnel Field-Effect Transistor with Epitaxially Grown Tunnel Junction Fabricated by Source/Drain-First and Tunnel-Junction-Last Processes

We fabricate p- and n-channel Si tunnel field-effect transistors (TFETs) with an epitaxially grown tunnel junction. In a novel source/drain-first and tunnel-junction-last fabrication process, a thin epitaxial undoped Si channel (epichannel) is deposited on a preferentially fabricated p- or n-type source area. The epichannel sandwiched by a gate insulator and a highly doped source well acts as a parallel-plate tunnel capacitor, which effectively multiplies drain current with an enlarged tunnel area. On the basis of its simple structure and easy fabrication, symmetric n- and p-transistor and complementary metal oxide semiconductor inverter operations were successfully demonstrated.

Investigation of Local Bending Stress Effect on Complementary Metal–Oxide–Semiconductor Characteristics in Thinned Si Chip for Chip-to-Wafer Three-Dimensional Integration

A three-dimensional LSI (3D-LSI) that vertically stacks Si chips with a number of through-silicon vias (TSVs) and metal microbumps has attracted much attention recently. However, there are some issues to be resolved in the fabrication of 3D-LSI. In this study, we investigated impacts of local bending stress on the performance of a complementary metal–oxide–semiconductor (CMOS) circuit fabricated in a thinned Si chip. First, we proposed a novel method and a test structure to easily induce the local bending stress in the thinned Si chip. Then, we evaluated the distribution of the local bending stress and its effects on the electrical characteristics of metal–oxide–semiconductor field-effect transistor (MOSFETs). As a result, we observed the degradations of the MOSFET currents and CMOS inverter switching behaviors in accordance with the chip local bending. Our experimental results obviously indicate that the local bending stress caused large fluctuations in the performance of the circuit fabricated in the thinned Si chip.