Complementary Metal-oxide-semiconductor Integrated Circuits Research Articles

New structure transistors for advanced technology node CMOS ICs.

Over recent decades, advancements in complementary metal-oxide-semiconductor integrated circuits (ICs) have mainly relied on structural innovations in transistors. From planar transistors to the fin field-effect transistor (FinFET) and gate-all-around FET (GAAFET), more gate electrodes have been added to three-dimensional (3D) channels with enhanced control and carrier conductance to provide higher electrostatic integrity and higher operating currents within the same device footprint. Beyond the 1-nm node, Moore's law scaling is no longer expected to be applicable to geometrical shrinkage. Vertical transistor stacking, e.g.in complementary FETs (CFET), 3D stack (3DS) FETs and vertical-channel transistors (VFET), for enhanced density and variable circuit or system design represents a revolutionary scaling approach for sustained IC development. Herein, innovative works on specific structures, key process breakthroughs, shrinking cell sizes and design methodologies for transistor structure research and development are reviewed. Perspectives on future innovations in advanced transistors with new channel materials and operating theories are also discussed.

Design and Fabrication of a Thin and Micro-Optical Sensor for Rapid Prototyping.

Optical sensing offers several advantages owing to its non-invasiveness and high sensitivity. The miniaturization of optical sensors will mitigate spatial and weight constraints, expanding their applications and extending the principal advantages of optical sensing to different fields, such as healthcare, Internet of Things, artificial intelligence, and other aspects of society. In this study, we present the development of a miniature optical sensor for monitoring thrombi in extracorporeal membrane oxygenation (ECMO). The sensor, based on a complementary metal-oxide semiconductor integrated circuit (CMOS-IC), also serves as a photodiode, amplifier, and light-emitting diode (LED)-mounting substrate. It is sized 3.8 × 4.8 × 0.75 mm3 and provides reflectance spectroscopy at three wavelengths. Based on semiconductor and microelectromechanical system (MEMS) processes, the design of the sensor achieves ultra-compact millimeter size, customizability, prototyping, and scalability for mass production, facilitating the development of miniature optical sensors for a variety of applications.

Monolithic Three-Dimensional Integration of Carbon Nanotube Circuits and Sensors for Smart Sensing Chips.

Semiconducting carbon nanotube (CNT) film is a promising material for constructing high-performance complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) and highly sensitive field-effect transistor (FET) bio/chemical sensors. Moreover, CNT logic transistors and sensors can be integrated through a compatible low-temperature fabrication process, providing enough thermal budget to construct monolithic three-dimensional (M3D) systems for smart sensors. However, an M3D sensing chip based on CNT film has not yet been demonstrated. In this work, we develop M3D technology to fabricate CNT CMOS ICs and CNT sensor arrays in two different layers; then, we demonstrate a preliminary M3D sensing system comprising CNT CMOS interfacing ICs in the bottom layer and CNT sensors in the upper layer through interlayer vias as links. As a typical example, a highly sensitive hydrogen sensing IC has been demonstrated to perform in situ sensing and processing functions through upper-layer FET-based hydrogen sensors exposed to the environment and bottom-layer CNT CMOS voltage-controlled oscillator (VCO) interfacing circuits. The M3D CNT sensing ICs convert hydrogen concentration information (8-128 ppm) to digital frequency information (0.78-1.11 GHz) with a sensitivity of 2.75 MHz/ppm. M3D sensing technology is expected to provide a universal sensing system for future smart sensing chips, including multitarget detection and ultralow power sensors.

Integrated Circuit Design of Fractional-Order Chaotic Systems Optimized by Metaheuristics

Nowadays, a huge amount of research is done on introducing and implementing new fractional-order chaotic systems. In the majority of cases, the implementation is done using embedded hardware, and very seldom does it use integrated circuit (IC) technology. This is due to the lack of design automation tools ranging from the system level down to layout design. At the system level, the challenge is guaranteeing chaotic behavior by varying all parameters while optimizing dynamical characteristics, such as the Lyapunov spectrum and the Kaplan–Yorke dimension. Using embedded hardware, the implementation is straightforward, but one must perform a scaling process for IC design, in which the biases may be lower than 1 volt but the amplitudes of the state variables of the chaotic systems can have values higher than one. In this manner, this paper describes three levels of abstraction to design fractional-order chaotic systems: The first one shows the optimization of a case study, the mathematical model of the fractional-order Lorenz system to find the fractional-orders of the derivatives, and the coefficients that generate better chaotic behavior. The second level is the block description of a solution of the mathematical model, in which the fractional-order derivatives are approximated in the Laplace domain by several approximation methods. The third level shows the IC design using complementary metal–oxide–semiconductor (CMOS) technology. The transfer functions approximating the fractional-order derivatives are synthesized by active filters that are designed using operational transconductance amplifiers (OTAs). The OTAs are also used to design adders and subtractors, and the multiplication of variables is done by designing a CMOS four-quadrant multiplier. The paper shows that the simulation results scaling the mathematical model to have amplitudes lower than ±1 are in good agreement with the results using CMOS IC technology of 180 nm.

Customized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs

The design and optimization of the analog complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are intrinsically complicated and depend heavily on the designer’s experience, and are associated with very long design and optimization-cycle times. In addition, in order to the analog and radiofrequency (RF) CMOS IC work suitably in practice, it is necessary to perform robustness analyses (RAs) through Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, which result in still-higher design and optimization cycle times and therefore represent the biggest bottleneck to the launching of new electronic products. In this context, this manuscript aims to present, for the first time, the use of a custom imperialist competitive algorithm (ICA) in order to reduce the design and optimization-cycle times of analog CMOS ICs. In this study, we implement some Miller CMOS operational transconductance amplifiers (OTAs) using the computational tool named iMTGSPICE, considering two different bulk CMOS IC manufacturing processes from Taiwan Semiconductor Company (TSMC) (180 nm and 65 nm nodes) and two evolutionary optimization methodologies of artificial intelligence, i.e., ICA and a genetic algorithm (GA). The main result obtained by this work shows that, by using an ICA-customized evolutionary algorithm to perform the design and optimization processes of Miller CMOS OTAs, it is possible to reduce the design and optimization-cycle times by up to 83% in relation to those implemented with the GA-customized evolutionary algorithm, achieving practically the same electrical performance.

Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs

Previous studies have been showing that the first generation of layout styles composed by the Diamond (hexagonal), Octo (octagonal) and Ellipsoidal gate shapes for implementing of the planar and three-dimensional MOSFETs are is capable of boosting their analog and digital electrical performances and also by reducing used die areas, when we replace conventional Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), that present rectangular gate shape, by those implemented by these innovative layout styles. In order to further boosting these features obtained by the use of first generation of layout styles, we are introducing one of elements of the second generation of layout styles for MOSFETs, intitled Half-Diamond. This new proposal is an evolution of Diamond layout style, in which it is able to preserve the Longitudinal Corner Effect (LCE), the Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivation of Parasitic MOSFETs in Bird’s Beaks Regions (DEMPAMBBRE) effects of the first generation and also of further reducing the dimensions of conventional MOSFETs (CM) in which the Diamond MOSFETs have gotten to do. Thus, this work performs an experimental comparative study between the electric performances of MOSFETs implemented with the Half-Diamond, Diamond and Conventional layout styles, regarding the analog Complementary MOS (CMOS) integrated circuits (ICs) applications, which their channel lengths are not usually designed with the minimum dimension (Lmin) allowed by the CMOS ICs manufacturing processes. The results obtained show that, for instance, the saturation drain current normalized by the aspect ratio and low-frequency open-loop voltage gain, in dB, of MOSFET implemented with the Half-Diamond layout style (HDM) are 17% and 3.5% higher, respectively, than those found in CM counterparts. Besides, by using Half-Diamond layout style, it is possible of further reducing the die areas of analog CM and consequently of the analog CMOS ICs applications, in comparison to those reached by the use of Diamond layout styles, regarding a 180 nm Bulk CMOS ICs technology node.

Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique

In this article, the design, fabrication and characterization of silicon carbide (SiC) complementary-metal-oxide-semiconductor (CMOS)-based integrated circuits (ICs) are presented. A metal interconnect strategy is proposed to fabricate the fundamental N-channel MOS (NMOS) and P-channel MOS (PMOS) devices that are required for the CMOS circuit configuration. Based on the mainstream 6-inch SiC wafer processing technology, the simultaneous fabrication of SiC CMOS ICs and power MOSFET is realized. Fundamental gates, such as inverter and NAND gates, are fabricated and tested. The measurement results show that the inverter and NAND gates function well. The calculated low-to-high delay (low-to-high output transition) and high-to-low delay (high-to-low output transition) are 49.9 and 90 ns, respectively.

The Impact of LCE and PAMDLE Regarding Different CMOS ICs Nodes and High Temperatures

This paper describes the influence of Longitudinal Corner Effect (LCE effect) and PArallel Connection of Metal–Oxide–Semiconductor Field-Effect Transistors (MOSFETs) with Different Channel Lengths Effect (PAMDLE effect) of Diamond (hexagonal gate shape) MOSFET in different Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) technologies (180nm-Bulk and $1\mu \text{m}$ -Silicon-On-Insulator, SOI) and in a wide range of high-temperatures (from 300K to 573K). The results have shown (average gains of Diamond MOSFET in relation to standard MOSFET: 60% for saturation drain current, 51% for transconductance, 10% for transconductance-over-drain current ratio etc.) that LCE and PAMDLE effects tend to be similar for CMOS ICs technological nodes used and the different high temperatures. Therefore, we can conclude, for the first time, that LCE and PAMDLE effects are kept active in different CMOS ICs technological nodes and when the Diamond MOSFET is exposed at high temperatures.

Methodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETs

This paper describes a pioneering methodology to design, optimize, and reduce the total gate area of robust Operational Transconductance Amplifiers (OTAs). The Single-Ended Single-Stage (SESS) OTA has been chosen to validate the proposed technique by using the 180 nm planar Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) technology. The Electronic Design Automationtool, named iMTGSPICE, was used to design and optimize the SESS OTA. There are several heuristics optimization techniques of Artificial Intelligence to optimize analog and radio-frequency CMOS ICs, but we have selected to use the Genetic Algorithm because it presents the best optimization performance among the other algorithms previously studied. This paper also describes a procedure of converting the Conventional planar MOSFETs (rectangular gate shape) into the Diamond MOSFETs (hexagonal gate shape) with the same electrical performance. Furthermore, it is proposed a procedure to simulate the Diamond MOSFETs (DMs) in the Simulation Program with Integrated Circuit Emphasis (SPICE) because there is still no SPICE model to perform the DM. Additionally, this work proposes a methodology to layout OTAs with Diamond MOSFETs, regarding different values of aspect ratios. The main result of this work reveals a total gate area reduction of approximately 30% of a robust OTA implemented with Diamond MOSFETs, with an alpha angle (α) equal to 45°, with respect to the one observed in the robust OTA implemented with standard MOSFETs, maintaining practically the same electrical performance and robustness.

Ultrasensitive Magnetic Sensors Enabled by Heterogeneous Integration of Graphene Hall Elements and Silicon Processing Circuits.

Graphene Hall elements (GHEs) have been demonstrated to be promising magnetic field sensors with excellent sensitivity, linearity, temperature stability, and compatibility with complementary-metal-oxide-semiconductor (CMOS)-integrated circuits (ICs). However, the demonstrated GHEs have still not exhibited a comprehensive advantage in performance over commercial integrated Hall sensors which were implemented in integrated Hall element and CMOS processing ICs. In this work, we develop a technology for the three-dimensional (3D) heterogeneous integration of silicon-based CMOS ICs and GHEs, and the fabricated magnetic field sensors outperform commercial high-end integrated Hall sensors. Specifically, the integrated Hall sensors are implemented in a stacked integration on Si based on a chopper programmable-gain amplifier (CPGA), a chopper-stabilized second-order sigma-delta modulator (CSDM), and graphene-based Hall elements on monochips. GHEs with high sensitivity (up to 1000 A/VT) are fabricated with a compatible process on a smoothened silicon nitride passivation layer of silicon-based CMOS ICs, and the two device layers are connected by an interlayer. The heterogeneous integrated Hall ICs exhibit current and voltage magnetic sensitivities up to 64 000 A/VT and 6.12 V/VT, respectively, which are much higher than those in all other reported nanomaterial-based Hall sensors and even in high-end commercial Hall ICs. Furthermore, the 3D heterogeneous integration technology used here can be extended as a universal technology for integrating nanomaterial-based sensors and Si CMOS ICs.

Strengthened Complementary Metal-Oxide-Semiconductor Logic for Small-Band-Gap Semiconductor-Based High-Performance and Low-Power Application.

Silicon-based complementary metal-oxide-semiconductor (CMOS) has been the mainstream logic style for modern digital integrated circuits (ICs) for decades but will meet its performance limits soon. Extensive investigations have thus been carried out using other semiconductors, especially those with extremely high carrier mobility. However, these materials usually have small or even zero band gap, which leads inevitably to large leakage current or voltage loss in ICs based on these semiconductors. In this work, we propose and demonstrate a strengthened CMOS (SCMOS) logic style using modified field-effect transistors (FETs) to solve this problem, that is, to achieve high performance, utilizing the high carrier mobility in these materials, and to reduce the current leakage resulting from their small band gap. Conventional CMOS FETs are modified to have an asymmetric structure where an additional assistant gate is introduced near the drain to further lower the potential barrier in on-state and to increase the barrier in off-state. SCMOS ICs are constructed using these modified asymmetric CMOS FETs, which demonstrate perfect rail-to-rail output with negligible voltage loss and 3 orders of magnitude suppression of the static power consumption and an operating speed similar to or even higher than that of CMOS ICs. Here, SCMOS is demonstrated using carbon nanotubes, but, in principle, this logic style can be used in ICs based on any small-band-gap semiconductors to provide simultaneously high performance and low power consumption.

Using the Octagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments

This article describes an experimental comparative study of the matching between the Octo conventional (octagonal gate geometry) and Conventional (rectangular gate shape) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) Integrated Circuits (ICs) technology and exposed to different X-rays Total Ionizing Doses (TIDs), under the on-state bias conditions. The results indicate that the Octo layout style with alpha ( $\alpha $ ) angle equal to 90° and a cut factor of 50% for MOSFETs is capable of boosting the device matching by at least 56.1%, on average, regarding the electrical parameters studied (Threshold Voltage and Subthreshold Swing), as compared to those found in the Conventional MOSFET counterparts, considering that they present the same bias conditions and regarding different TIDs. This happens due to the Longitudinal Corner Effect (LCE), Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) which are present in the Octo MOSFETs. Therefore, the Octagonal layout style can be considered as an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio-frequency CMOS ICs applications.

Radiation-Hard and Repairable Complementary Metal-Oxide-Semiconductor Circuits Integrating n-type Indium Oxide and p-type Carbon Nanotube Field-Effect Transistors.

Special radiation-hard and ultralow-power complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are used in the fields of deep space, nuclear energy, and medical X-ray imaging. In this work, we first constructed radiation-hard, repairable, and sub-1 V-driven printed hybrid CMOS field-effect transistors (FETs) and ICs, which integrate printed carbon nanotube (CNT) (band gap ∼ 0.65 eV) p-type FETs and indium oxide (In2O3) (band gap ∼3.64 eV) n-type FETs on glass substrates using a printed PS-PMMA/[EMIM][TFSI] mixture as the gate dielectric layer. The PS-PMMA/[EMIM][TFSI] mixture gate dielectric layer not only lowered the supply voltage (VDD) by providing ultrahigh gate efficiency but also improved the anti-irradiation ability of the hybrid CMOS FETs and ICs. Specifically, the hybrid CMOS inverters exhibited rail-to-rail output with a high voltage gain and high noise margins at a low VDD that could be scaled down to 0.4 V. Furthermore, the hybrid CMOS FETs and ICs showed excellent radiation hardness, that is, withstanding a 3 Mrad (Si) total irradiation dose (TID) at a dose rate of 560 rad s-1 (Si), which is an exceptional result for CMOS transistors and ICs. Furthermore, the radiation-damaged CMOS FETs could be fully recovered by removing and reprinting the PS-PMMA/[EMIM][TFSI] mixture gate dielectric layer, indicating the ability to repair irradiation damage. This work provides an in-space IC fabrication technology.

Using the Hexagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments

This paper describes an experimental comparative study of the matching between conventional (rectangular gate shape) and Diamond (hexagonal gate geometry) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) technology and exposed to different X-rays Total Ionizing Doses (TIDs). The results indicate that the Diamond layout style with alpha () angle equal to 90˚ for MOSFETs is capable of boosting the device matching by at least 17% regarding the electrical pa-rameters studied (Threshold Voltage and Subthreshold Slope) as compared with the conventional MOSFET counterparts, considering that they present the same gate area, channel width, bias conditions and for the same TID. This is due to the Longitudinal Corner Effect (LCE). Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) present in the structure of Diamond MOSFETs. Therefore, the Diamond layout style can be consid-ered an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio-frequency CMOS inte-grated circuits (ICs) applications.

Design for High Reliability of CMOS IC With Tolerance on Total Ionizing Dose Effect

As the standard complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) generates a leakage current due to ionizing radiation reacting with silicon in a radiological environment, radiation hardening of CMOS devices is being actively investigated. If a radiation-tolerant IC (RTIC) is designed, it is very important to examine the design possibility of an application specific IC (ASIC) that uses a radiation-tolerant MOS field-effect transistor (MOSFET). This study developed a new RTIC design using an I-gate structure that is more effective in terms of time, cost, and reliability than the existing RTMOSFET. Because an RTIC with an I-gate structure can be fabricated via the usual full-custom IC design process, it can be produced after its reliability is ensured based on post-layout simulation results, which are obtained by layout parasitic extraction (LPE). To realize the possibility of such fabrication, radiation-tolerant digital and analog ICs were designed and fabricated in the standard 0.18- $\mu \text{m}$ CMOS process, and an irradiation test was conducted up to a total dose of approximately 2 Mrad. Accordingly, the radiation damage in the standard IC and the radiation tolerance of the RTIC were identified. Consequently, we have proposed and verified an efficient radiation-tolerant ASIC design solution.

New Radiation-Hardened Design of a CMOS Instrumentation Amplifier and its Tolerant Characteristic Analysis

A radiation-hardened instrumentation amplifier (IA) that allows precise measurement in radiation environments, including nuclear power plants, space environments, and radiation therapy rooms, was designed and manufactured, and its characteristics were verified. Most electronic systems are currently designed using silicon-based complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs) to achieve a highly integrated low-power design. However, fixed charges induced in silicon by ionization radiation cause various negative effects, resulting in, for example, the generation of leakage current in circuits, performance degradation, and malfunction. Given that such problems in radiation environments may directly lead to a loss of life or environmental contamination, it is critical to implement radiation-hardened CMOS IC technology. In this study, an IA used to amplify fine signals of the sensors was designed and fabricated in the 0.18 μm CMOS bulk process. The IA contained sub-circuits that ensured the stable voltage supply needed to implement system-on-chip (SoC) solutions. It was also equipped with special radiation-hardening technology by applying an I-gate n-MOSFET that blocks the radiation-induced leakage currents. Its ICs were verified to provide the intended performance following a total cumulative dose of up to 25 kGy(Si), ensuring its safety in radiation environments.

Mechanical and Electrical Reliability Analysis of Flexible Si Complementary Metal-Oxide-Semiconductor Integrated Circuit.

A flexible Si complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) with multi-level interconnects is realized by thinning down and transferring the CMOS IC onto a polymer substrate. A detailed mechanical and electrical reliability analysis of the flexible Si CMOS IC is carried out in relation to the neutral mechanical plane (NMP) that is extracted from both analytical and numerical modeling. To enhance the reliability by optimizing the NMP position, the thicknesses of all the layers in the CMOS IC on the polymer substrate are carefully adjusted. The NMP-optimized flexible Si CMOS IC maintains its mechanical and electrical stability even at a 5-mm radius bending condition. In addition, to explore the degradation mechanism of the flexible Si CMOS IC, the change of the interface state density of the flexible Si CMOS at different bending conditions is investigated using the charge pumping method. Finally, the long-term electrical reliability of this flexible Si CMOS IC is also investigated.

A customized genetic algorithm with in-loop robustness analyses to boost the optimization process of analog CMOS ICs

The traditional optimization processes of analog complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are very complex, slow, and based on the designers’ experience. To obtain robust potential solutions, it is necessary to perform robustness analyses (RAs) through SPICE simulations. However, this approach represents a huge bottleneck in the optimization processes due to the significant increase of time of the SPICE simulations concerning the RAs. Therefore, this work proposes an innovative customized genetic algorithm (GA) to boost the optimization process of analog CMOS ICs. The main results obtained showed that all designs of analog CMOS ICs reached a yield of 100% and a remarkable reduction of the optimization time (from 23% to 79%) in comparison with the standard optimization process with the GA, without reducing the random samples number considered in the RAs, and consequently preserving their robustness accuracy.

Silicon nanowires to detect electric signals from living cells

The ability to merge electronic devices with biological systems at the cellular scale is an interesting perspective. Potential applications span from investigating the bio-electric signals in excitable (and non-excitable) cells with an insofar-unreached resolution to plan next-generation therapeutic devices. Semiconductor nanowires are well suited for achieving this goal because of their intrinsic size and wide range of possible configurations. However, production of such nanoscale electrodes can be pricey, time-consuming and affected by poor compatibility with the Complementary Metal-Oxide-Semiconductor integrated circuits (CMOS-IC) process standards. To take a step forward, we introduced a new method to fabricate small, high-density Silicon Nanowires (SiNWs) with a fast, relatively inexpensive and low-temperature (200 °C) process compatible with CMOS-IC standards, thus theoretically allowing on-site amplification of bioelectric signals from living cells in tight contact. Here, we report our preliminary data showing the biocompatibility of SiNWs, as a necessary step to produce a compact device providing super-resolved descriptions of bioelectric waveforms captured from the subcellular to the network level.

Impact of designer knowledge in the interactive evolutionary optimisation of analogue CMOS ICs by using iMTGSPICE

This Letter describes an innovative interactive evolutionary computational tool to optimise robust analogue complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs), by using genetic algorithm, entitled iMTGSPICE. The main results demonstrate that the iMTGSPICE is able to reduce the optimisation cycle times of designs of robust single-ended single-stage and Miller operational transconductance amplifiers (OTAs) in up to 93.9% in comparison to the non-interactive optimisation process. Moreover, the iMTGSPICE is capable of reducing the influence of the knowledge levels of the analogue CMOS ICs designers (experts and non-experts) to obtain robust potential solutions (maximum error of 0.5% for the Miller OTA).