Complement Number System Research Articles

Design Space Exploration Based Methodology for Residue Number System Digital Filters Implementation

In the past decades, the Residue Number System (RNS) has been adopted in DSP as an alternative to the traditional two’s complement number system (TCS) because of the savings in area and power dissipation. In this work, we first perform a comprehensive Design Space Exploration (DSE) to analyze the impact of state-of-the-art design tools and libraries on the implementation of the basic operations (i.e., addition and multiplication) used in DSP. From this DSE, we extract the characteristics of the stand-alone RNS and TCS operators in the different design corners, independently of the specific context of the application. Then, we propose a design methodology, based on the DSE, to fully automate the design of digital filters, hiding the detail of the RNS to the designer, and providing optimal power efficient implementations. Our methodology can enable the efficiency in computation (speed and power) in DSP and in emerging applications, such as Machine Learning and Internet-of-Things.

Residue Number Systems: A New Paradigm to Datapath Optimization for Low-Power and High-Performance Digital Signal Processing Applications

Residue Number System (RNS) is a non-weighted number system which was proposed by Garner back in 1959 to achieve fast implementation of addition, subtraction and multiplication operations in special-purpose computations. Unfortunately, RNS did not turn out as a popular alternative to two?s complement number system in those days. The rigidity of instruction set architectures of the market-dominant computers and microprocessors then has been the main barrier to sustain the development of RNS-based applications. In recent years, technological advancement in semiconductor technology has revived the interests to reconsider RNS for application-specific computing. There are at least two unique motivations which make RNS computations more attractive and applicable in modern digital signal processing applications. Firstly, the modular and distributive properties of RNS are used to achieve performance improvements especially in the emerging distributed and ubiquitous computing platforms such as cloud, wireless ad hoc networks, and applications which require tolerance against soft error. Secondly, energy efficiency becomes a key driver in the continual densification of complementary metal oxide semiconductor (CMOS) digital integrated circuits. The high degree of computational parallelism in RNS offers new degree of freedom to optimize energy performance, particularly for very long word length arithmetic such as those involved in the hardware implementation of cryptographic algorithms. Our aim in this paper is to show this revolution by discussing interesting development in RNS and foster the innovative use of RNS for more applications. Different applications of RNS are investigated to demonstrate how this unconventional number system can be leveraged to benefit their implementation.

An FPGA realization of simplified turbo decoder architecture

The key issue of applying Turbo codes is to find an efficient implementation of turbo decoder. This paper addresses the implementation of a simplified and efficient turbo decoder in field programmable gate array (FPGA) technology. A simplified and efficient implementation of a Turbo decoder with minor performance loss has been proposed. An integer Turbo decoder based on the standard 2’s complement number system after considering the issues of dynamic range, truncation effect and other algorithm related subjects has been introduced. The efficient implementation comes from algorithm modification, integer arithmetic and compact hardware management. Based on the Max-Log-MAP decoding algorithm, the branch metric is modified by weighting a priori value, resulting in a significant BER improvement. The Turbo decoder takes in 8-level integer inputs generates 7-bit soft-decisions and calculates all metrics on integers, avoiding complex floating point or fixed-point arithmetic. By manipulating memory address, delay associated with interleaving and de-interleaving is eliminated, resulting in much higher throughput. Also, by taking advantage of identical decoder function, Turbo decoder is implemented in a single-decoder structure, making efficient use of memory and logic cells. Key words: Turbo, Max-Log-MAP, field programmable gate array, bit error ratio.

The Negative Two’s Complement Number System

The two's complement fractional fixed-point number system is widely used to implement digital signal processing on VLSI chips. It has a range of values from ?1 to one least significant bit below +1. Either the multiplication of ?1 ? ?1 or taking the absolute value of ?1 produces a result (+1) that cannot be represented. A new system, the negative two's complement number system, is described here that has a range of one least significant bit above ?1 to +1 which eliminates the problem. This paper presents the new number system and describes algorithms for the basic arithmetic operations.

Bit-serial, MSB first processing units

This paper introduces three new bit-serial designs for the arithmetic operations of division, square-root and multiplication. The designs are novel in that they adopt the same 2's complement number system, operate on a most significant bit first data stream and use a data interleaving scheme to achieve high throughput. The communication of data between the designs is streamlined, with a minimum of control and conversion circuitry required. This allows the architectures to be used in conjunction with high speed analogue-to-digital conversion techniques such as pipelined ADCs and successive approximation ADCs. These high speed ADCs are required in complex DSP algorithms such as parametric spectral estimation, where the three arithmetic functions of multiplication, division and square-root are also required.

Quantization error analysis of the radix-4 signed-digit arithmetic

The quantization error characteristics of the signed-digit arithmetic are studied for the application to the MSD (Most Significant Digit) first digit serial computation, where only truncation is allowed for the word-length reduction of the multiplied results. This study shows that truncated results in the signed-digit arithmetic contain very little DC error when a symmetric remainder reduction scheme is employed. The error characteristics are similar to those of the rounding scheme in the two's complement number system. However, the symmetric remainder reduction scheme demands more hardware and delay than the asymmetric reduction scheme.

Comments, on "A signed bit-sequential multiplier" by T. Rhyne and N.R. Strader II

With reference to the above mentioned paper (see ibid., vol.C-35, p.896-901 (1986)), it is stated that the authors' introduction, in which they claim that the references all deal with algorithms for processing unsigned operands, is erroneous. One of their references most certainly does not deal with unsigned operands, as a two's complement number system is one of the module interfacing conventions germane to R. Lyon's (1981) methodology. Moreover, in the authors' conclusions they state that they 'have now extended bit-sequential multiplication to signed, two's complement binary operands', which may give the (doubtless unintended) impression that this has not been done before.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

On a Bit-Serial Input and Bit-Serial Output Multiplier

A recent paper by Chen and Willoner [1] forwarded a bit-sequential input and output (LSBfirst) multiplier for positive numbers. This multiplier for n-bit operands requires 2n clocks and 2n number of five-input adder modules. In this correspondence, after a brief discussion on the different claims made by the authors of [1] and their limitations, we show that this multiplier can be realized with only n adder modules. The technique is extended to two's complement number system. Also, a more complete picture of the actual implementation is depicted. Finally, we bring to the attention an already existing multiplier which fits into the bit-sequential multiplier category.

Comment on the Sequential and Indeterminate Behavior of an End-Around-Carry Adder

The sequential and indeterminate behavior of an end-around-carry (EAC) adder is examined. This behavior is commonly overlooked in the literature. Design modifications to impose determinism are provided. These modifications also eliminate the troublesome negative zero found in the one's complement number system.