Comparator Circuit Research Articles

Impact of increasing post-filter ionised calcium target on regional citrate anticoagulation efficacy in ICU continuous renal replacement therapy: the non-inferiority randomised controlled Ca-CIBLE protocol

IntroductionContinuous renal replacement therapy (CRRT) is a critical therapeutic intervention for patients with severe acute kidney injury in intensive care. However, premature filter clotting remains a significant challenge during CRRT,...

A common-mode insensitive thyristor-based latch regenerative comparator for low supply voltage applications

Presented in this article is a new two-stage rail-to-rail regenerative comparator circuit designed for low supply voltage applications. This work introduces a thyristor-based latch for the first time, allowing the comparator to operate from rail-to-rail inputs. The proposed comparator has been post-layout simulated using a standard 65 nm CMOS technology. The worst-case simulation results demonstrate that the comparator exhibits a delay of less than 22ns and consumes only 132 nW of power at a supply voltage of 0.6V and a sample rate of 1 MHz across its full common-mode range. Furthermore, the total input-referred offset voltage (3std + mean) remains below 21 mV throughout the entire rail-to-rail common-mode voltage range. Compared to the conventional single-stage comparator, the proposed circuit showcases an improvement of over 87 % in terms of delay and energy efficiency. Given its dignified performance metrics, this comparator is well-suited for use in low supply voltage applications such as biomedical implants, successive approximation registers analog-to-digital converters (SAR ADCs), Internet of Things (IoT).

An efficient new design of nano-scale comparator circuits using quantum-dot technology

Traditional semiconductor-based technology has recently faced many issues, such as physical scalability constraints and short-channel properties. Much research on nano-scale designs has resulted in these flaws. Quantum-dot Cellular Automata (QCA) is a promising nanotechnology solution for solving CMOS-related issues. The 4-dot squared cell is identified as the main feature of this technology. Also, a comparator is an essential electronic device that compares 2 voltages or currents. It is frequently employed to confirm whether an input has achieved a predefined value or not. So, the design of the QCA-based comparator is one of the interesting lines in recent studies. However, cell and area consumption limits the circuit design in the most relevant research. As a result, two efficient comparator circuits based on the inherent rules of quantum dots have been presented in this work. The proposed 1-bit design employs 35 quantum cells in a 0.04 μm2 compact layout space. Also, the proposed 2-bit design uses 173 cells in a 0.19 μm2 compact layout area. These circuits, which are built across three layers of 90-degree cells, remove the need for coplanar crossovers, ensuring accessible inputs and outputs. The presented 1-bit comparator circuit uses 3 majority gates with three inputs. The first output signal in 1-bit comparator is generated after 0.75 clock phases and in 2-bit design after 1.25 clock phases. QCADesigner-E evaluated the suggested circuits' practical accuracy, cost, and power. The results showed that the proposed designs are extremely efficient in cell and area consumption compared to the state-of-the-art designs.

Efficient Taste Analysis via Single-Channel Hybrid Electronic Tongue

The prospective applications of electronic tongues (e-tongues) in the food, water, beverage, and pharmaceutical industries have long been hampered by the inconvenient nature of series measurements using expensive and specialised sensor arrays. A cost-efficeint and easier solution to this problem arises in the shape of a single-channel hybrid e-tongue, presenting a novel approach to overcoming restrictions. This progress uses data fusion from potentiometry and impedimetry to combine these measures into a single channel made up of unfunctionalized metal electrodes supported by a pH electrode.The hybrid e-tongue combines potentiometric response, which includes pH and open circuit potential, with impedimetric response, which takes into account comparable electric circuit parameters such as charge transfer resistance and double-layer capacitance. The taste discriminability of this low-cost single-channel hybrid e-tongue is validated using two metal electrodes, Pt and Ni, and two separate sample preparations of basic taste analytes, each at concentrations around the human tongue threshold.Principal component analysis (PCA) plots are used to test qualitative discrimination by reducing dimensionality and clustering analytes. Silhouette coefficients (SC) and hierarchical cluster analysis are used to assess clustering quality. Even without particular sample preparation, the Pt and Ni electrodes exhibit substantial clustering with SC values of 0.83 and 0.74, respectively. This significant outcome highlights the efficacy of the hybrid e-tongue in improving taste discriminability.Comparisons with potentiometric and impedimetric measurements performed independently show that the hybrid e-tongue, assisted by data fusion at a single channel, improves accuracy and clustering significantly. This finding not only speeds up the analysis process, but it also improves the overall effectiveness of taste discrimination.Correlations between taste analytes and physicochemical factors are formed using heatmap plots and PCA loading plots to provide a fuller knowledge of the hybrid e-tongue's mechanics. These visualisations provide vital insights into the complex interplay of several physicochemical processes, offering insight into the mechanism underlying the hybrid e-tongue's excellent performance.discrimination.Despite its remarkable capabilities, the study acknowledges that taste discriminability diminishes due to the buffer activity of the standard reference solution used for sample preparation. This recognition prompts further exploration and optimization of the solution to ensure the broad applicability of the hybrid e-tongue across various scenarios.In conclusion, the reported single-channel hybrid e-tongue represents a significant advancement in taste analysis technology. By addressing the challenges associated with series measurements on complex sensor arrays, this innovation opens new avenues for commercial e-tongues in diverse industries. The amalgamation of potentiometry and impedimetry in a single channel not only enhances accuracy and clustering but also provides valuable mechanistic insights. As the research community continues to refine and optimize this technology, the future holds great promise for the widespread adoption of single-channel hybrid e-tongues in analytical applications, advancing how we perceive and understand taste.

A novel design of hysteretic comparator circuit towards GaN-based power IC

This paper proposes a hysteretic comparator circuit employing a positive feedback loop composed of all N-type devices towards GaN-based power integration circuits. By combining a source follower with comparator, the proposed hysteretic comparator circuit avoids the dependence on resistors, thus improving the integration density. To demonstrate the novelty, feasibility, and advantages of the proposed circuit, not only GaN-based but also Si-based circuits are investigated by simulations in ADS and Cadence, respectively. Simulated by the cadence virtuoso tool using TSMC 180 nm technology, it exhibits a layout area of 171.08 μm2, signal gain of 55.74 dB at low frequency, and maximum static power dissipation of 364.6 μW when the power supply is 3.3 V. In addition, it's verified that a signal gain of 55.11 dB at low frequency, transition time of 0.2 ns, and maximum static power dissipation of 2.064 W when the power supply is 12 V are achieved in GaN-based circuit according to simulation results in ADS. Consequently, compared with other mainstream or previously reported circuit in the same conditions, more ideal working performance and compact size are achieved by the proposed circuit, providing an advantageous strategy for monolithically integrating hysteretic comparator circuit in GaN-based power IC.

Simplified 1.5 μm Distributed Feedback Semiconductor Laser (DFB-LD) Frequency Stabilization System Based on Gas Absorption Chamber

The classical 1.5 μm band frequency-stabilized laser using acetylene gas saturated absorption can achieve high frequency stability and reproducibility, but its system design is complex and bulky. For some practical applications, a simple, compact system containing anti-interference abilities is preferred. In this study, a low-cost and simple-structured 1.5 μm frequency-stabilized laser is constructed using digital control methods, wavelength modulation technology, and acetylene gas absorption. The fiber input and output optical devices of the system significantly simplify the optical path and reduce the volume of the system. The error signal is obtained by the first-order differential method, and a combination of the high-speed comparator circuit and the microcontroller unit (MCU) is used to detect the error signal. Through the feedback control method of coarse temperature adjustment and fine current adjustment, the second-level frequency stability of the laser is stabilized within 100 kHz, that is, the frequency stability reaches 10​−10. The designed system achieved continuous and stable operation for more than 6 h, and the long-term frequency stability reached 10​−9.

Silicene/BN heterostructure as high-performance anode material for Mg-ion batteries

Finding a suitable anode material is a key part of the development of Mg-ion batteries (MIBs) to commercialize. In this work, an outstanding Silicene/BN heterostructure was discovered as a candidate anode material for MIBs by using first-principles calculations. The mixed sp2/sp3 orbital hybridization of silicon atoms makes Silicene monolayer easy to adsorb Mg atoms. The introduction of BN monolayer can effectively buffer the structural deformation and improve the electrochemical performances. Compared to pristine Silicene, the Silicene/BN heterostructure exhibited higher structural stability and Mg adsorption capacity. The diffusion of Mg ions in the heterostructure interlayer was easier with a low barrier of 0.160 eV than that on the Silicene monolayer. A comparable low open circuit voltage (0.112 V) was also observed. These results indicated the potential of Silicene/BN heterostructure as a high-performance anode material for MIBs.

Improving photon number resolvability of a superconducting nanowire single-photon detector array using a level comparator circuit

Photon number resolving (PNR) capability is very important in many optical applications, including quantum information processing, fluorescence detection, and few-photon-level ranging and imaging. Superconducting nanowire single-photon detectors (SNSPDs) with a multipixel interleaved architecture give the array an excellent spatial PNR capability. However, the signal-to-noise ratio (SNR) of the PNR (SNRPNR) of the array will be degraded with increasing the element number due to the electronic noise in the readout circuit, which limits the PNR resolution as well as the maximum PNR number. In this study, a 16-element interleaved SNSPD array was fabricated, and the PNR capability of the array was investigated and analyzed. By introducing a level comparator circuit (LCC), the SNRPNR of the detector array was improved over a factor of four. In addition, we performed a statistical analysis of the photon number on this SNSPD array with LCC, showing that the LCC method effectively enhances the PNR resolution. Besides, the system timing jitter of the detector was reduced from 90 ps to 72 ps due to the improved electrical SNR.

An Enhanced Strong ARM Comparator Circuit for Analog to Digital Converter Architectures

Abstract: Technological innovations in the current century period have motivated professionals to make electronic gadgets smarter. These advancements are progressing at a brisk pace, facilitating faster changes and increase in computing power. Various technologies such as virtual reality, augmented reality, mobile internet, artificial intelligence, cloud computing, biometric devices, 3D printing machines, genomics, quantum computing, block-chain, industrial automation and robotics. In all these technologies, communications with nearby devices play a major role in its effective functioning. The demand for realizing a smart and better usage experience puts forth strict requirements on the design aspects of next-generation high speed low power CMOS receiver design. One of the major modules in the implementation of high speed low power CMOS receiver device is the analog to digital converter (ADC) architecture. In the process of conversion from analog to digital signals, Quantization and sampling operations are vital and are realized using comparator circuits. The comparator design has a significant role in the design of data converter architecture. Several comparator architectures exist, but StrongARM topology is discussed and implemented in this work due to its negligible static power dissipation and rail to rail output voltages. The proposed novel comparator architecture is designed and simulated in 180nm CMOS process using Cadence Virtuoso tool and operated at supply voltage of VDD=1.8V, a clock frequency of 50MHz

Lowering the cost of quantum comparator circuits

Quantum comparators hold substantial significance in the scientific community as fundamental components in a wide array of algorithms. In this research, we present an innovative approach where we explore the realm of comparator circuits, specifically focussing on three distinct circuit designs present in the literature. These circuits are notable for their use of T-gates, which have gained significant attention in circuit design due to their ability to enable the utilisation of error-correcting codes. However, it is important to note that T-gates come at a considerable computational cost. One of the key contributions of our work is the optimisation of the quantum gates used within these circuits. We articulate the proposed circuits employing Clifford+T gates, facilitating error correction code implementation. Additionally, we minimise T-gate usage, thereby reducing computational costs and fortifying circuit robustness against errors and environmental disturbances-essential for mitigating the effects of internal and external noise. Our methodology employs a bottom-up examination of comparator circuits, initiating with a detailed study of their gates. Subsequently, we systematically dissect the functions of these gates, thereby advancing towards a comprehensive understanding of the circuit’s overall functionality. This meticulous examination forms the foundation of our research, enabling us to identify areas where optimisations can be made to improve their performance.

A Low-Power Analog Integrated Euclidean Distance Radial Basis Function Classifier

This study introduces a low-power analog integrated Euclidean distance radial basis function classifier. The high-level architecture is composed of several Manhattan distance circuits in connection with a current comparator circuit. Notably, each implementation was designed with modularity and scalability in mind, effectively accommodating variations in the classification parameters. The proposed classifier’s operational principles are meticulously detailed, tailored for low-power, low-voltage, and fully tunable implementations, specifically targeting biomedical applications. This design methodology materialized within a 90 nm CMOS process, utilizing the Cadence IC Suite for the comprehensive management of both the schematic and layout design aspects. During the verification phase, post-layout simulation results were meticulously cross-referenced with software-based classifier implementations. Also, a comparison study with related analog classifiers is provided. Through the simulation results and comparative study, the design architecture’s accuracy and sensitivity were effectively validated and confirmed.

The Window Comparator Circuit with CMOS and TTL Logic ICs Switching levels

The Window Comparator Circuit with CMOS and TTL Logic ICs Switching levels

A Rail-To-Rail and Low Offset Novel Strongarm Comparator Circuit for Low Power Data Converter Architectures

With the rapid improvements in the design of advanced high performance communication receivers, hand-held electronic devices are in widespread usage for some time. These devices facilitate high speed and secured access to internet data. The demand for realizing a smart and better usage experience puts forth strict requirements on the design aspects of next-generation high speed low power complementary metal oxide semiconductor (CMOS) receiver design. One of the major modules in the implementation of high speed low power CMOS receiver device is the analog to digital converter (ADC) architecture. In the process of conversion from analog to digital signals, Quantization and sampling operations are vital and are realized using comparator circuits. The comparator design has a significant role in the design of data converter architecture. Several comparator architectures exist, but StrongARM topology is discussed and implemented in this work due to its negligible static power dissipation and rail to rail output voltages. The proposed novel comparator architecture is designed and simulated in 90nm CMOS process using Cadence Virtuoso tool and operated at supply voltage of VDD=1.5V, a clock frequency of 250MHz. Compared to the previous designs, the energy delay product was reduced by 8% which is an important observation to be observed for use in wireless sensor node applications.

Enhancing Surface Electromyography (sEMG) Signal Processing through a Four-bit Absolute Value Comparator

This paper delves into the realm of Surface Electromyography (sEMG) signal processing, presenting a comprehensive exploration of its theoretical underpinnings and the application of a four-bit absolute value comparator. The journey commences with an introduction to the subject matter, followed by an in-depth analysis of the theoretical basis of sEMG signals, encompassing their definition and waveform characteristics, as well as the processing flow. The focal point of this study is the utilization of a four-bit absolute value comparator in enhancing sEMG signal processing. Moving forward, the paper delves into the intricacies of logic circuit design, elucidating the architecture of both adder and comparator circuits pivotal in this context. Circuit optimization strategies are subsequently unveiled, addressing critical path considerations, gate sizing, and VDD optimization to bolster efficiency. In summation, this research advances our understanding of sEMG signal processing and introduces a novel four-bit absolute value comparator, which holds promise in elevating the precision and reliability of sEMG data analysis.

Optimal Design of Two-Bit QCA Comparator Circuits

Optimal Design of Two-Bit QCA Comparator Circuits

Flower-shape resonator-based triple-band metamaterial wave absorbers to find the dispersion relation utilizing one dimensional (1-D) periodic waveguide

This paper proposes a flower-shape resonator-based triple band with a high-performance metamaterial wave absorber to find the dispersion relation utilizing one dimensional (1-D) periodic waveguide. The proposed absorber comprises flower-shaped square split ring resonator-based resonators separated by a Rogers RT5870 (lossy) dielectric layer with a thickness of 1.575 mm and back annealed copper with 0.035 mm thickness, and the size of the unit cell is 8 mm × 8 mm. The outcomes of simulations conducted using the Computer Simulator Technology (CST) Microwave Studio simulator reveal the presence of three absorption peaks at frequencies of 5.032, 7.96, and 13.94 GHz with an absorption of 99.709%, 99.966%, and 99.973%, respectively. As a result, this work presents a substitute concept in terms of phase velocity of mode in limited with periodic arrangements, showing it determines the type with terms of modalities a one-dimensional periodic concave parallel plates wavelength. The suggested phase velocity has been analysed using simulations using the CST Microwave Studio simulator and the CST eigenmode solver. A comparable circuit analysis demonstrates the superior performance of the metamaterial wave absorber, indicating its potential for excellent functionality within the advanced design system (ADS) software. Additionally, the proposed structures, modelled with the High-Frequency Structure Simulator (HFSS), exhibit a close correspondence with the maximum absorbance observed at each resonance peak in CST simulation results. The proposed research demonstrates excellent features such as unity absorption, angle insensitivity, and more, making it highly suitable for dispersion relation as well as C, X, and Ku band applications.

Design and Application SCR Trigger Circuit for Three-phase Half-wave Controlled Rectifier with Resistive Load

Power electronics is a field of science that studies and discusses electronics applications related to large-power electrical equipment, one of the sub-subject studied is the AC to DC converter such as a three-phase half-wave controlled rectifier with a resistive load in which output voltage can be controlled by adjusting the triggering delay angle of gate SCR. The components used include a three-phase step-down transformer where the output is used as a reference signal to determine the starting point (30o) and the endpoint (150o) of triggering delay angle, it is also used as a power source for the system, LM393 is used as a comparator between three-phase rectifier (Vd) with DC voltage (Vreference), likewise to compare triangular waves with DC voltages that resulting from changes in the voltage on the potentiometer in order to control the triggering delay angle (α) of SCR. The first step that must be taken to make measurements using an oscilloscope is to determine the ton and toff values for each angle by rotating the potentiometer on the comparator circuit and then measuring the average output voltage (Vo), determination the triggering angle in this research is still done manually so that the measurement results compared to the calculation has a difference this is due to the level of accuracy in observing the oscilloscope, on the other hand, the three-phase transformer and sources used are not in ideal conditions.

Threshold Inverter Quantizer (TIQ)-Based 2-Bit Comparator Using Spatial Wavefunction Switched (SWS) FET Inverters

A Threshold Inverter Quantizer (TIQ)-based voltage comparator is used to quantize analog input signal in flash ADC designs. This quantizer is based on the systematic sizing of CMOS inverter thus eliminating resistor array which is used for conventional comparator array. Such an implementation removes static power during quantization of analog input signal. This paper presents a simulation of TIQ 2-bit-based comparator using spatial wavefunction switched (SWS) field effect transistor (FET)-based CMOS inverters. The inverters use 4-state SWSFETs. Unlike conventional FETs, SWSFETs consist of two or more vertical coupled arrays of either quantum dot or quantum well channels, where the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10), and (11). The TIQ-based comparator circuit presented here is based on the 2-bit SWS-CMOS inverter. The schematic of the ADC comparator circuit is demonstrated as well as the 2-bit ADC configuration cascading two 2-bit SWSFET-based inverters in CMOS-X. The circuit simulation was done in Cadence and SWSFET was modeled by integrating Berkeley Short-Channel IGFET Model (BSIM) and the Analog Behavioral Model (ABM). The 2-bit comparator circuit provides a four-state logic output voltage for any given analog input signal.

Study of Ionization Radiation Effects in Digital Circuits for Aerospace Application

Combinational standard cells based on the RHBD approach and using 180 nm technology with Cadence Virtuoso are the focus of this work effort. Radiation from space, heavy ions, and radioactive particles (protons, neutrons) pose the greatest threat to integrated circuits (ICs).Single Event Transients (SETs), a serious issue for digital semiconductor design, are caused by ever reduced feature sizes and declining supply voltage. The three proposed C-element based cells under investigation are inverter, NAND gate, and buffer. The Cadence Virtuoso programme was used to create their schematics. RHBD-based circuit designs are more tolerant of Single Event Effects (SEE), better at resisting noise, and consume less static power. Less static power is used in RHBD-based circuit designs, which also have better noise resistance. For the other C-element-based logic circuits, the Noise Margin is likewise enhanced in comparison to the comparable conventional circuits.

An X-shaped triple split ring resonator-based metamaterial perfect absorber with quad-band incident and polarization angle insensitivity for C, X, and Ku band applications

In this study, an X-shaped triple split ring resonator-based metamaterial perfect absorber with quad-band incident and polarization angle insensitivity for C, X, and Ku band applications has been proposed. The metamaterial perfect absorber consists of a prearrangement with metallic patch, metal ground plane and a middle Rogers RT5870 dielectric substrate with 1.575 mm thickness. The numerical methods implemented using finite integration technology (FIT) demonstrate that the metamaterial perfect absorber (MPA) exhibits an absorption capacity exceeding 99% in all frequency bands, precisely matching the impedance of free space. These frequency bands are located at 4.37 GHz, 7.08 GHz, 9.38 GHz, and 10.65 GHz with the absorption levels of approximately 99.8%, 99.9%, 99.9%, and 99.9% respectively for both transverse electric (TE) and transverse magnetic (TM) modes. Additionally, the MPA demonstrates quality factors of 21.92, 7.2, 13.42, and 15 for both modes. The investigation of the electromagnetic (EM) field with surface current distribution has provided information about the mechanism of such quad-band absorbance. The numerical analysis reveals that the metamaterial perfect absorber (MPA) can achieve remarkable absorbance outcomes across a wide range of incident angles, up to 800s, while also being insensitive to polarization up to 300 for both modes. A comparable circuit analysis demonstrates the superior performance of the MPA, indicating its potential for excellent functionality within the advanced design system (ADS) software. Furthermore, the suggested structures, modelled using the high-frequency structure simulator (HFSS), closely align with the maximum absorbance observed at each resonance peak in the computer simulator technology (CST) simulator results. The proposed MPA possesses high-performance characteristics that enable its application in various domains such as satellite communications, raw satellite feeds, and radar systems.