Comparator Circuit Research Articles

WITHDRAWN: A 4-Bit 1GS/s Folding Flash ADC using 45-nm CMOS Technology

Abstract This paper presents a design of 4 bit folding Flash ADC using 3 bit Flash with 45 nm CMOS technology. A novel design of Folding network for Flash ADC to reduce the complexity of comparator circuit is proposed. Sampler circuit , MSB and LSB comparators are designed and verified. Mismatches are introduced in the circuit and the simulations results are presented with and without mismatches for the Maximum sampling frequency of 1GS/s. 4 bit ADC performance is compared with three different input frequencies. The results parameters are compared with other topologies. Overall system have the power consumption 2.9mW with the ENOB of 3.87@29 Mhz with the 1V supply voltage.

Low-energy X-ray performance of SOI pixel sensors for astronomy, “XRPIX”

We have been developing a new type of X-ray pixel sensors, “XRPIX”, allowing us to perform imaging spectroscopy in the wide energy band of 1–20keV for the future Japanese X-ray satellite “FORCE”. The XRPIX devices are fabricated with complementary metal-oxide-semiconductor silicon-on-insulator technology, and have the “Event-Driven readout mode”, in which only a hit event is read out by using hit information from a trigger output function equipped with each pixel. This paper reports on the low-energy X-ray performance of the “XRPIX6E” device with a Pinned Depleted Diode (PDD) structure. The PDD structure especially reduces the readout noise, and hence is expected to largely improve the quantum efficiencies for low-energy X-rays. While F-K X-rays at 0.68keV and Al-K X-rays at 1.5keV are successfully detected in the “Frame readout mode”, in which all pixels are read out serially without using the trigger output function, the device is able to detect Al-K X-rays, but not F-K X-rays in the Event-Driven readout mode. Non-uniformity is observed in the counts maps of Al-K X-rays in the Event-Driven readout mode, which is due to region-to-region variation of the pedestal voltages at the input to the comparator circuit. The lowest available threshold energy is 1.1keV for a small region in the device where the non-uniformity is minimized. The noise of the charge sensitive amplifier at the sense node and the noise related to the trigger output function are ∼18e− (rms) and ∼13e− (rms), respectively.

Precise phase control of resonant MOEMS mirrors by comb-drive current feedback

Accurate phase detection and control of nonlinear resonant micro-opto-electro-mechanical system (MOEMS) mirrors are crucial to achieve stable scanning motions and high resolution imaging as needed in precision applications. This paper proposes a precise phase detection method for an electrostatic actuated MOEMS mirror and a novel digital phase locked loop (PLL) that uses an asynchronous logic for high precision driving and immediate phase compensation, while the clock speed is kept low. The phase of the mirror is detected by an amplified current signal, generated by the movement of the comb drive electrodes, transimpedance amplifiers and a simple comparator circuit. An analysis of the proposed detection method reveals that the pointing uncertainty scales with the product of the driving voltage, the curvature of the comb drive capacitance and the angular velocity of the MOEMS mirror at the zero crossing. The developed fast start-up procedure brings the MOEMS mirror to its maximum amplitude within less than 100 ms with a minimum on required prior knowledge of the used device. The low optical pointing uncertainty of 0.3 mdeg obtained in closed loop operation, allows 19000 pixels with a precision of 10 sigma at a scanning frequency of 2 kHz.

Design of Low Power & Area Efficient of 8-Bit Comparator using GDI Technique

In this paper we are design a circuit based on data selector and distributor networks in which we will not realize the circuit based upon the expressions but off course the circuit which have designed will have internally some expression. In the recent trends the need for low power and less on-chip area is on high note for the portable devices. In this project we want to focus on the design constraints of VLSI. Innovative design of 8-Bit GDI based Comparator will be proposed and implemented. Optimization depends on selection of GDI Cell as well as selection of primary inputs to the terminals of GDI cell. 8-Bit GDI based Comparator will be designed and simulated using Tanner EDATool. Comparator has three main outputs where it can compare the weight of two words and generates three functions. GDI has the advantage of low power consumption because the total number of logic devices needed willbe less and it can also operate with high speed due to affective realization of logic using minimal hardware. Comparator circuits is designed using tanner tools and also observe the simulation results in H-SPICE attaining low power and less delay.

Machine Learning-Based Approach for Hardware Faults Prediction

Hardware failures are undesired but a common problem in circuits. Such failures are inherently due to the aging of circuitry or variation in circumstances. In critical systems, customers demand the system never to fail. Several self-healing and fault tolerance techniques have been proposed in the literature for recovering a circuitry from a fault. Such techniques come to the rescue when a fault has already occurred but they are typically uninformed about the possibility of an impending failure (i.e., fault prediction), which can be used as a pre-stage to fault tolerance and self-healing. This paper presents an approach to early fault prediction of circuits. The proposed method uses Fast Fourier Transform (FFT) to get the fault frequency signature, Principal Component Analysis (PCA) to get the most important data with reduced dimension, and Convolutional Neural Network (CNN) to learn and classify the fault. The proposed method is validated for working in different circuits by testing it using two circuits: comparator and amplifier. The comparator and amplifier are implemented using 45 nm technology on HSPICE to extract the failures dataset in terms of voltage, current, temperature, noise, and delay. This extracted data is used for training the proposed approach using Tensorflow. To the best of our knowledge, this is the first work of fault prediction at the transistor level for hardware system. The proposed approach considers aging, short-circuit, and open-circuit faults, and it provides a fault prediction accuracy of 98.93% and 98.91% for comparator and amplifier circuits, respectively. The proposed method is tested for two different circuits for its validation, and it consumes 1.08 W for Altera Arria 10 GX FPGA device.

Analysis the several Techniques in designing the comparators for ADC converter and Introduction the CMOS Comparator Circuit with low power and high speed suitable for Medical Equipments

Analysis the several Techniques in designing the comparators for ADC converter and Introduction the CMOS Comparator Circuit with low power and high speed suitable for Medical Equipments

Multi-level swell voltage control for minimizing the damage to an on-grid system

This article presented multi-level swell voltage control for minimizing the damage to an on-grid system between 1.3 to 1.8 pu. in compliance with the value regulated by IEEE and IEC standards. A window comparator circuit and comparator circuit with hysteresis transistor were used as the voltage detector and the excessive pulse entering the multi-level control of the load. According to the designed function in every stage in the form of fail-safe AND gate, the system was set for this case by turning to the fail-safe mode in order to prevent a fail-dangerous mode that might harm the electric system if the device in the detection circuit is deprived of qualification which is against the condition. Due to the Failure Mode and Effect Analysis (FMEA) in accordance with IEC-6196-1, the function prevents the electric and electronic devices of the on-grid system from damage. The design and installation of the electric protection device SVSS has a parallel-connect with the electric system without the concern of the load’s current.

Multi-level swell voltage control for minimizing the damage to an on-grid system

This article presented multi-level swell voltage control for minimizing the damage to an on-grid system between 1.3 to 1.8 pu. in compliance with the value regulated by IEEE and IEC standards. A window comparator circuit and comparator circuit with hysteresis transistor were used as the voltage detector and the excessive pulse entering the multi-level control of the load. According to the designed function in every stage in the form of fail-safe AND gate, the system was set for this case by turning to the fail-safe mode in order to prevent a fail-dangerous mode that might harm the electric system if the device in the detection circuit is deprived of qualification which is against the condition. Due to the Failure Mode and Effect Analysis (FMEA) in accordance with IEC-6196-1, the function prevents the electric and electronic devices of the on-grid system from damage. The design and installation of the electric protection device SVSS has a parallel-connect with the electric system without the concern of the load’s current.

A New Nano Design for Implementation of a Digital Comparator Based on Quantum-Dot Cellular Automata

Quantum-dot is the result of elastic relaxation which has a straight relationship with the optical and electronic aspects of the quantum-dot-based devices. In nanotechnologies, Quantum-dot Cellular Automata (QCA) is a perfect transistor-less computation method where it tries to create general computation at the nanoscale with better switching frequency and enhanced scale integration to overcome the scaling shortfalls of CMOS technology. In this technology, binary information is represented based on the distribution of electron configuration in chemical molecules. Also, the comparator is the essential component in digital circuits, which takes two binary numbers as input and implements their resemblance. In this paper, a 1-bit comparator architecture in an optimized and efficient manner is suggested to bring a new phase of comparator circuit based on QCA, and then a novel 2-bit comparator structure is offered. The simulation and functionality of proposed comparators have been examined by the QCAdesigner tool, and comparison with formerly designs shows a high degree of compactness and consistent performance of proposed designs. Proposed 1-bit and 2-bit QCA comparators exhibit a delay of 0.75 and 2.75 clock cycle, occupy an active area of 0.04 and 0.19 μm2, and use 31 and 125 QCA cells, respectively.

Spurious radiation suppression in microstrip monopulse antenna

Purpose This paper aims to introduce a new novel microstrip monopulse comparator system to reduce the spurious radiation from the comparator and the feed network for achieving better radiation performance. Design/methodology/approach Two substrate layers have been used for the microstrip monopulse comparator system. The feed network and the comparator circuits are on the first substrate layer and the microstrip array antenna is on the second layer. The elements of the array antenna are novel square four-sided narrow rectangular slot antennas built on a conducting plane. A commercially available computational software, CST microwave studio, has been used for the analysis of the system. Findings Two substrate layers have been used for the microstrip monopulse comparator system. The feed network and the comparator circuits are on the first substrate layer and the microstrip array antenna is on the second layer. The elements of the array antenna are novel square four-sided narrow rectangular slot antennas built on a conducting plane. A commercially available computational software, CST microwave studio, has been used for the analysis of the system. Practical implications The system is proposed for tracking moving targets. Originality/value Novel slot radiators are introduced as radiating elements in this paper. The antenna arrangement shields the comparator and the feed network circuits, reducing the spurious radiation significantly.

Application of Multi-Stage Window Comparator Circuit with Safety Mode for Swell Voltage Control in Low Voltage Systems

Application of Multi-Stage Window Comparator Circuit with Safety Mode for Swell Voltage Control in Low Voltage Systems

Transmitting and Receiving Ultrasound Wave Based on Laser Light

Our project was divided into two distinct sections, circuit transmitting and receiving ultrasoundWave Based on Laser Light. A Wien Bridge and a Triangle Wave Oscillators used to obtain a sineand a triangular wave, respectively. A comparator circuit which produces Pulse Width Modulation(PWM) that has the same frequency for triangle wave. The PWM was used to drive laserdiode that produced laser light through by MOSFET transistor and received this light by receivingcircuit which consists of a photodiode with resistor as a voltage divider, amplifier circuit to amplifythe signal and filter to get any desired frequency. The main objective of this project primarilywas to realize a transmission-reception system to transfer ultrasound Frequency via Laser withouta guiding medium, using modulation with little quality loss.

Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC

This paper presents a highly efficient ternary flash ADC, designed using the innovative gate-overlap tunnel FET (GOTFET) at the 45 nm technology node. The proposed GOTFETs have on-state currents Ion more than double, while the off-state currents Ioff remaining at least an order of magnitude lower than the corresponding values of the standard 45 nm CMOS technology with the same width. Replacing MOSFETs with the proposed GOTFETs significantly reduces the static power consumption and improves performance. However, the higher Ion increases the dynamic power as well. To minimize the dynamic power, we propose a novel complementary GOTFET (CGOT) based comparator design. In addition to the inherent advantages of the GOTFET technology, the proposed design further reduces the dynamic power, such that the final power delay product (PDP) is merely 6.3% of the PDP in conventional CMOS comparator design. In addition to the novelty related to the innovative GOTFET devices, there are at least two-fold circuit-level novelty reported in this work. Firstly, we propose a novel CGOT based comparator circuit design, which, in addition to the advantages of GOTFET, further reduces the dynamic power such that the PDP is less than 1/3rd of the original PDP of the conventional comparator designed with GOTFETs. Secondly, the proposed CGOT based ADC requires only 48 transistors to encode the comparator outputs into the 2-bit ternary output, which is 30% lower than the 70 transistors necessary for the 2-bit CMOS based ternary flash ADC designs reported earlier in the literature. We propose an efficient 2-bit ternary flash ADC with a resolution of 50 mV and input quantized to 9 levels. Subsequently, we benchmark the performance of the proposed CGOT ternary flash ADC with the same ADC circuit implemented using the standard 45 nm CMOS technology library, all corresponding devices having the same width. We demonstrate that in addition to the superior performance than the corresponding CMOS ADC, the proposed CGOT ADC design consumes significantly lower power. The overall PDP of the proposed CGOT ADC is merely 6.3% of the PDP in corresponding CMOS design.

An Energy Efficient Binary Magnitude Comparator for Nanotechnology Applications

Quantum-dot cellular automata (QCA) is inventive nanotechnology that suggest lesser size, lesser power consumption, with more rapid speeds and deliberated as a clarification to the scaling difficulties with CMOS technology. Physical bounds of CMOS for instance the effects of quantum and the limits of technologies like power dissipation obstruct the motion of microelectronics using consistent circuit scaling. In this paper, a 1-bit binary magnitude comparator circuit is proposed that takes down the count of QCA cells related to the previously reported design’s cell numbers. The proposed course of study involves just around 29 % of the total area as compared to the preceding design with the lesser speed and clocking cycle performance and energy dissipation also. QCA designerE tool is used for simulation and finding the parameters also. The projected magnitude comparator also compares the metrics result with some of the other preceeding patterns.

Spin—Based voltage comparator using spin-hall effect driven nanomagnets

In this work, we propose a spin-based voltage comparator using a hybrid spin-CMOS circuit model. In particular, we use a 3T-MTJ (three-terminal magnetic tunnel junction) model with an in-plane magnetic anisotropy (IMA) free layer employing a spin-orbit torque (SOT) based writing scheme in the thermal activation regime to demonstrate a comparator circuit with a resolution close to 50mV. The 3T-MTJ model of the comparator was validated against existing experimental results. In addition, we analyze the delay performance of the comparator along with matching the switching delay of the MTJ with an analytical model. We also discuss potential extensions to the model and general directions for future work.

Low Power 11T Adder Comparator Design

Comparator is a basic arithmetic component in a digital system and adders are the basic block of processor unit, the performance of adder will improve the system performance. The proposed 11T adder comparator is consists of three main components, namely XOR, inverter, and MUX logic. The circuit is designed and implemented based on top-down approach with 11 transistors. The proposed cell can be used at higher temperature with minimal power loss. It also gives faster response for the carry output. The proposed comparator circuit shows 63.80% improvement in power consumption than other circuits.

Design of 10 Bit ADC of SAR Type to Increase the Accuracy for Biomedical Applications

In this paper a low power consuming 10 bit SAR ADC which is suitable for Biomedical applications is presented. It was designed with 180nm technology using cadence tool. SAR ADC is made of dynamic comparator, sample and hold circuit, SAR logic, and DAC block. The designed circuit works on a supply voltage of 1V. The proposed SAR design, with the use of dynamic comparator circuit will help to reduce power and even at the same time with the use of binary weighted CDAC also provides low power dissipation. In order to decide the next significant bit by the knowledge of previous bits the successive approximation algorithm runs over several clock cycles for analog to digital conversion. Power usage and complexity of the circuit is minimized by low conversion rate i.e permitting one clock for each bit in the proposed method.

Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation

Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC). This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed. The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V. The method used to verify the robustness of the comparator circuit across 45 PVT is presented. The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 100°C. The simulation result show that the proposed comparator circuit achieved significant reduction of power consumption and delay during worst case condition compared to dynamic comparator proposed from previous researchers.

Adaptive maintain power signature scheme for power over ethernet system

Power over Ethernet (PoE) technology has been widely used in networking market for its space-saving, flexibility and low cost. As the PoE system needs to meet maintain power signature (MPS) requirements specified by the IEEE standard, it is important for powered device (PD) to draw a predetermined minimum current. If the PD current goes below the minimum current, the power sourcing equipment (PSE) assumes the PD has been disconnected and terminates operating voltage. If a fixed current is added to exceed the minimum current, a phenomenon of power wasting will be caused during standby or ultra-low power mode. This study proposes an adaptive MPS scheme to achieve power-saving and meet the MPS requirements. It consists of current comparator and MPS circuit to extract the periodic pulsed current for MPS requirements. The proposed scheme has been fabricated in 0.18 μm 100 V Bipolar-CMOS-DMOS process adding no extra pin and an area is 1.45 × 2.23 mm2. Test results show that the proposed interface sources a periodic pulsed current with a period of 318 ms and 25% duty cycle to tackle the issue of MPS absence in very low power condition.

EIS comparative study and critical Equivalent Electrical Circuit (EEC) analysis of the native oxide layer of additive manufactured and wrought 316L stainless steel

In this work, a comparative electrochemical impedance spectroscopy (EIS) study of the native oxide layer of selective laser melted and wrought 316L stainless steel is conducted. A careful examination of the data is carried out in order to properly identify the appropriate model to fit the EIS response. From the parameters calculated by fitting the EIS data and a complementary XPS analysis, the electrical and dielectric characteristics of the passive oxide layers of the specimens were obtained. Clear differences were noticed between the two materials, which could definitely contribute to the overall understanding of the corrosion behavior of these materials.