A novel design of hysteretic comparator circuit towards GaN-based power IC

Abstract

This paper proposes a hysteretic comparator circuit employing a positive feedback loop composed of all N-type devices towards GaN-based power integration circuits. By combining a source follower with comparator, the proposed hysteretic comparator circuit avoids the dependence on resistors, thus improving the integration density. To demonstrate the novelty, feasibility, and advantages of the proposed circuit, not only GaN-based but also Si-based circuits are investigated by simulations in ADS and Cadence, respectively. Simulated by the cadence virtuoso tool using TSMC 180 nm technology, it exhibits a layout area of 171.08 μm2, signal gain of 55.74 dB at low frequency, and maximum static power dissipation of 364.6 μW when the power supply is 3.3 V. In addition, it's verified that a signal gain of 55.11 dB at low frequency, transition time of 0.2 ns, and maximum static power dissipation of 2.064 W when the power supply is 12 V are achieved in GaN-based circuit according to simulation results in ADS. Consequently, compared with other mainstream or previously reported circuit in the same conditions, more ideal working performance and compact size are achieved by the proposed circuit, providing an advantageous strategy for monolithically integrating hysteretic comparator circuit in GaN-based power IC.