Compaction Scheme Research Articles

A multiple signature compaction scheme for BIST

The approach of checking multiple signatures has recently received attention because of the associated advantages of small aliasing, easy computation of fault coverage, shorter average test time, and increased fault diagnosability. In this paper we propose a BIST multiple-signature compaction scheme that achieves negligibly small aliasing against reasonable extra hardware expenses compared with known standard single signature schemes and against less expenses than those incurred by other “low aliasing probability” schemes. Experimental results illustrate possible tradeoffs between the number of signatures, their width (number of bits) and hardware requirements.

The analysis of digital integrators for test response compaction

The compaction properties of integrators that could be used in the built-in self-test (BIST) environment instead of linear finite-state-machine-based comparators are studied. Markov chain models are used to provide a quantitative characterization of the compaction scheme in terms of its steady-state behavior as well as its transient properties. It is demonstrated that the asymptotic fault coverage drop depends on the fault injection site, the fault injection probability, and the gain factor. A simple modification of the standard integrator is also proposed in order to improve the quality of compaction. The proposed scheme introduces very small hardware overhead. It is compatible with the width of the data path, and the test can be applied at the normal mode speed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Performance of signature analysis: a survey of bounds, exact, and heuristic algorithms

Built-in self-test (BIST) is emerging as one of the most promising solutions for testing large and complex integrated circuits. In BIST, high test quality is generally achieved by applying a large number of test patterns to the circuit under test. The large amount of ensueing test response data makes test response compaction mandatory in most cases. Response compaction implies an information loss that translates into the possibility that a faculty circuit be declared good. Such an erroneous diagnosis is known as being caused by an aliasing error. For any BIST compaction scheme, it is crucial to have a measure of the possible aliasing. The scheme for performing compaction that has thus far received the most attention is known as signature analysis, which is implemented using linear feedback shift registers. Several papers on the probability of aliasing associated with signature analysis, under various error models, have recently been published. Alternative approaches have been proposed for computing such probabilities, ranging from computationally intensive exact solutions, to bounds, and approximate heuristic solutions. Here, we present a survey of these recent contributions and emphasize their important similarities and differences, thus enabling the user/designer of signature analysis-based schemes to make more efficient and knowledgeable use of them. We focus on single-input signature analysis, but also review recent results pertaining to multiple-input signature analysis.

Analysis of Hamming count compaction scheme

Advances in VLSI technology require changes in circuit test application methods or apparatus. The use of on-chip testing, called Built-in Testing or Built-in Self-Testing (BIST), has become popular. BIST techniques compact the output response of the circuit under test (CUT). Here we discuss a time compaction method called Hamming count (H-count). H-count encompasses all syndrome detectable faults. Simulation results and theoretical analysis illustrate the overall fault-detection potential of Hamming count. The proposed method presents simple and effective compaction technique. Since BIST methods use productive chip area, a prime concern is providing the test results using the minimal amount of space. Hardware overhead reduction through counter elimination is considered for the Hamming Count compaction test. Intelligent counter selection is necessary to minimize the impact this hardware reduction has on fault detection. A method for selecting the most advantageous syndrome and input variable counter combination to utilize as a reduced H-count test is introduced. Analysis shows that the proposed method produces an optimal pairing. The paired counters have an aliasing probability which is half an order less than that of an unmodified syndrome test with exhaustive inputs. Adaptations in the counter selection method are made using a greedy strategy for choosing multiple counters to combine with the syndrome counter.

Combined probabilistic testability calculation and compact test generation for PLAs

PLAs (programmable logic arrays) may be tested internally by self-test, or externally by applying test patterns. Fault coverage by nonexhaustive self-test is assured by computing a lower bound for estimated fault coverage vs. test pattern number. First, a lower bound for probabilistic detectability per fault is computed by a method based on Shannon's expansion theorem. In the process of finding a lower bound detectability for a particular fault, a test pattern for the fault is generated automatically, at no extra cost. These patterns often contain several don't cares. Traditional test pattern compaction is then applied to the test pattern set. In addition, a novel test pattern compaction method is introduced, suitable for embedded circuitry. The method may be used in conjunction with a serial scan architecture, whereby each test pattern is shifted one position before being applied to the circuit under test. The compaction scheme was applied to a benchmark set of 53 PLAs. An average reduction of 70% in the number of test bits and clock cycles was achieved.1

Using a multiple storage quad tree on a hierarchical VLSI compaction scheme

A graph-generating algorithm and the experimental results of a hierarchical mask-layout-compaction scheme based on a plane-sweep algorithm, a fast region-query and a space-efficient data structure called the hierarchical multiple-storage quad tree are presented. For a mask-layout design, a rectangle is used as the primary element of the layout. Hence, in the hierarchical mask-compaction scheme, the graph-generating algorithm is based on the edges of rectangles rather than the central lines of symbols for the symbolic-compaction design. The plane-sweep algorithm is also called a dynamic event scheduling algorithm and can be applied to solve some other problems in the field of computational geometry and image processing. The efficiencies of the plane-sweep algorithm and the graph-generating algorithm are dependent on the region-query operations of the spatial data structure. By using the improved multiple storage quad tree as the spatial data structure in the system, the mask-layout compactor has been accomplished in a practically linear time performance in terms of the rectangles in the source layout.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Using hierarchical multiple storage quad trees on a constraint‐graph layout compaction

Abstract In the last decade several primitives of quad trees have been proposed as data structures for the hierarchical design of VLSI. This paper presents algorithms, implementation, and experimental results of a hierarchical mask layout compaction scheme based on a fast region‐query and space‐efficient data structure called the hierarchical multiple storage quad tree. Contrary to symbolic compaction, this mask layout compaction is based on rectangle edges rather than symbols. A new method for the generation of a constraint‐graph is proposed in detail by using an alternative dynamic event scheduling algorithm (DES algorithm) in 2‐D space. This is a new plane sweep method based on the multiple storage quad tree and is capable of being extended to support the inherent problems in computational geometry and image processing. Some important features of the mask layout compactor: such as error‐tolerance, mixed‐constraint, grid‐freeness, and hierarchical design and amalgamation, are described in this article. ...

A new framework of design rules for compaction of VLSI layouts

A general framework for describing design rules is provided that encompasses space rules, size rules, extension rules, conditional rules, nonpositive rules, and minimum-type and maximum-type rules. Conditional rules considered include topological rules, width rules, and length rules. A fast compaction scheme was developed to handle this variety of rules in an efficient and uniform way. A compactor based on this approach was constructed that can handle several IBM technologies. In one CMOS technology, there are two width rules and two dozen topological rules, in addition to a hundred or so simple rules. The runtime performance data for several design examples, obtained on an IBM 3090 machine, are presented. It is noted that the use of conditional rules increases the computation cost only slightly, while it saves a significant amount of cell area compared with using all simple rules.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A time projection chamber data acquisition system

A data acquisition system is described which is used to digitize the trajectory information obtained in a time projection chamber. The time projection chamber is part of a spectrometer used to study the momentum spectrum of positrons emitted in muon decay. It has 315 sense wires which induce signals on 5355 pads and creates approximately 402 000 bits of data for each event. Most of the data are zeros which are handled using a hardware-aided compaction scheme. The meaningful data are extracted by a modular system consisting of three basic building blocks. These are flash encoders with associated storage, wire hit memory boards, and bit-slice data preprocessors described herein.

Interactive Cloud Formation and Climatic Temperature Perturbations

Abstract A one-dimensional climate model with an interactive cloud formation program is developed to investigate its effects on temperature perturbations due to various radiative forcings including doubling of CO2, a 2% increase of the solar constant and the increase of the cirrus IR emissivity. By virtue of the K-theory for turbulence transfer of sensible and latent heat flux we demonstrate that the model may be described by a set of partial differential equations governing the thermodynamic energy balance, water vapor transport, vertical velocity in the cloudy region and cloud cover. In particular, we illustrate that the climatic temperature perturbation experiment may be carried out as a boundary value problem. Moreover, in order to effectively incorporate interactive cloud formation and radiative transfer programs in the model, we have designed a cloud compaction scheme based on statistical and stochastic procedures for the estimate of cloud covers, thicknesses, heights and positions for high, middle ...

Performance analysis of compaction techniques for map representation in geographic databases

A new compaction scheme for representing cellular thematic maps in geographic databases is presented. The memory saving provided by this method, called Hierarchical Compaction Scheme (HCS) is analyzed and compared to that of two more classical cellular schemes. HCS not only provides a significant compaction ratio but also renders processing operations such as map intersection or union easier. It also allows the use of variable scale.

Data Acquisition System for a Time Projection Chamber

A data acquisition system has been designed to digitize the trajectory information of muon decay every eight milliseconds. A time projection chamber is used which operates in a solenoidal magnetic field. It has 315 sense wires which induce signals on 5355 pads and thus create approximately 402,000 bits of data for each event or 55 megabits per second. Most of the data are zeros which are handled using a hardware-aided compaction scheme. The meaningful data are extracted by a modular system consisting of three basic building blocks. These are flash encoders with associated storage, wire hit memory boards, and bit-slice data preprocessors described herein.

An Efficient Parallel Approach To ReduceSparse Matrices With Invariant Entries

This paper investigates an efficient parallel technique for reducing sparse matrices that can be applied to analysis tables. This kind of matrices take up a great amount of memory space by the zero entries and, hence, a subtle compaction scheme is necessary. The benefit of the parallel approach introduced herein is that a very compact form results which will contribute to a greatly reduced time when accessing the given data structure.