Compact Device Models Research Articles

IGZO TFT Backplane Integration for µLED Flat-Panel Display

The focus of this work is the process integration of Indium Gallium Zinc Oxide (IGZO) transistors as a µLED backplane for row/column addressing. A single pixel is composed of a µLED driven by an arrangement of two transistors and a storage capacitor. The pixels are then arrayed on a glass substrate to support active-matrix control of monochrome and full color (RGB) displays from 1x1cm (50 x 50 pixels) up to 7.6 x 7.6 cm (380 x 380 pixels). Optimization of circuit parameters considering size and scan frequency was modeled using existing TFT and µLED electrical device compact models. New process parameters and procedures were determined for the proper integration of µLEDs in an existing TFT fabrication process. Red, green, and blue µLED devices were fabricated at Tyndall National Institute on native substrates and were transferred to TFT pixels using an X-Display MTP-1003 micro-transfer printer. The performance of individual test cells was assessed using an Agilent B1500, revealing a voltage transfer characteristic indicating the ability to modulate and control µLED current.

Training-Free Parameter Extraction for Compact Device Models Using Sequential Bayesian Optimization With Adaptive Sampling

Training-Free Parameter Extraction for Compact Device Models Using Sequential Bayesian Optimization With Adaptive Sampling

Electric-Force Conversion Performance of Si-Based LiNbO3 Devices Based on Four Cantilever Beams.

In micron or nano smart sensing systems, piezoelectric cantilever beams are distributed as major components in microsensors, actuators, and energy harvesters. This paper investigates the performance of four cantilever beam devices with "electric-force" conversion based on the inverse piezoelectric effect of lithium niobate (LiNbO3, LN) single-crystal materials. A new compact piezoelectric smart device model is proposed, designed as a single mass block connected by four beams, where devices exhibit smaller lateral errors (0.39-0.41%). The relationship between the displacement characteristics of cantilever beams and driving voltage was researched by applying excitation signals. The results show that the device has the maximum displacement at a first-order intrinsic frequency (fosc = 11.338 kHz), while the displacement shows a good linear relationship (R2 = 0.998) with driving voltage. The square wave signals of the same amplitude have greater "electrical-force" conversion efficiency. The output displacement can reach 12 nm, which is much higher than the output displacement with sinusoidal excitation. In addition, the relative displacement deviation of devices can be maintained within ±1% under multiple cycles of electrical signal loading. The small size, high reliability, and ultra-stability of Si-LN ferroelectric single-crystal cantilever beam devices with lower vibration amplitudes are promising for nanopositioning techniques in microscopy, diagnostics, and high-precision manufacturing applications.

Compact modeling of metal–oxide TFTs based on the Bayesian search-based artificial neural network and genetic algorithm

Thin-film transistors play an important role in ultra-high definition displays. The conventional physical model requires a significant amount of time and resources, while its generalizability is limited. This paper introduces a method for quickly incorporating the characteristics of emerging devices into circuit simulations using an artificial neural network (ANN) model. The multi-layer perceptron (MLP) model, with a simple structure and high modeling efficiency, is employed as a typical ANN model. The pivotal step in using the MLP model is to determine its topology. This hyperparameter problem can be easily solved using Bayesian search. To improve the accuracy of the model, a genetic algorithm is proposed to optimize the initial values of the weights and biases. Furthermore, by introducing the first derivative in the loss function, small signal parameters can be taken into consideration. This modeling approach significantly reduces the time required for compact device modeling. Our experimental results exhibit a strong correlation between the model’s output and the corresponding experimental data, thereby providing comprehensive validation for the effectiveness of our proposed model. Once the trained model parameters were extracted, we implemented the hybrid ANN model using Verilog-A. This circuit-level experiment demonstrates that this hybrid ANN model can accurately estimate various physical devices and circuits.

Pragmatic OxRAM compact model ready to use for design studies

We propose a pragmatic OxRAM device compact model describing SET, RESET, read operations and accounting for variability. The model is implemented in Verilog-A and usable with standard SPICE simulator. The objective is not to provide physical insights into OxRAM device operation but to develop a robust model, simple to calibrate and accounting for the main effect for design studies. It includes the dependency of Low Resistive State (LRS) resistance with compliance current, and of High Resistive State (HRS) resistance with the programming voltage: the proposed model is able to describe multi-level OxRAM. Switching time variation with programming voltages for SET and RESET operations is also included. It is validated on HFO2 OxRAM device through the measurements of isolated 1 T-1R structures and 16 kb matrixes.

A novel methodology for neural compact modeling based on knowledge transfer

This work presents a novel approach of using knowledge transfer to increase the accuracy of artificial neural network (ANN)-based device compact models, or neural compact models. This is useful when the amount of data available for training an ANN is limited. By utilizing relatively abundant data of a previous technology node, physical phenomena that are not evident in the limited data of the target technology node (e.g. gate-induced drain leakage) are accurately predicted. When meta learning algorithms are used, the accuracy of the model significantly increases, with relative linear error 10 times lower compared to the case when prior knowledge is not incorporated. The proposed methodology can be used to model future generation devices with limited data, utilizing data from well-characterized past technology node devices.

Compact and Energy-Efficient Forward-Biased PN Silicon Mach-Zehnder Modulator

A compact device model along with simulations and an experimental analysis of a forward-biased PN junction-based silicon Mach-Zehnder modulator (MZM) with a phase-shifter length of 0.5 mm is presented. By placing the PN junction to a certain off-center such that 72% of the waveguide is p-doped, the refractive index swing at a given drive voltage swing is increased by 2% compared to the symmetric layout. The effects of the phase shifters’ length mismatch and asymmetric splitting on the modulation efficiency and extinction ratio of the modulator are simulated and compared with experimental results. Without any pre-emphasis or post-processing, a high-speed operation up to 15 Gb/s using a non-return-to-zero modulation format is demonstrated. A modulation efficiency ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${{\boldsymbol{V}}_{\boldsymbol{\pi}}}{\boldsymbol{L}}$</tex-math></inline-formula> ) as low as 0.07 V × cm is verified and power consumption of 0.88 mW/Gb/s is recorded while a high extinction ratio of 33 dB is experimentally demonstrated. Compared to previously reported forward-biased silicon integrated modulators, without active tuning of the power splitting ratio between the arms, the extinction ratio is 10 dB higher. This MZM along with its compact structure is also sufficiently energy-efficient due to its low power consumption. Thus, it can be suitable for applications like analog signal processing and high-order amplitude modulation transmissions.

RRAM Compact Modeling Using Physics and Machine Learning Hybridization

Machine learning (ML)-based compact model (CM) provide an alternative way in contrast to physics-based CMs. The advantages of ML CMs include the process-aware capability, expandability, improved behavioral model for a circuit block, and usability for emerging devices. On the other hand, while ML is on the rise, device physics can provide many guidelines in constructing ML CMs. Here, we propose a physics architecture in ML CMs for resistive random access memory (RRAM). The results show that the physics-assisted architecture enables simpler ML models in reference to our previous work of long short-term memory (LSTM)-based RRAM CMs. We found that the discrete state variable with classification is the best model to describe the RRAM set/reset scenario in multistep prediction problems. For the discrete and continuous state variables, the root mean square error (RMSE) on test data is 0.000125 and 0.000119, respectively. In addition, we demonstrate that the transient behavior of set/reset changes can be easily incorporated into the proposed model. Finally, the Verilog-A and HSPICE on a 1T1R cell have also been shown to prove the model feasibility. We suggest that the uniform framework with hybridization in physics and ML should be the most efficient way in future compact device modeling. The code is available at <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://github.com/albertlin11/RRAMunif</uri> .

Transistor Compact Model Based on Multigradient Neural Network and Its Application in SPICE Circuit Simulations for Gate-All-Around Si Cold Source FETs

Transistor compact model (TCM) is the key bridge between process technology and circuit design. Typically, TCM is desired to capture the nonlinear device electronic characteristics and their high-order derivatives. However, for the novel devices in advanced and future technologies, establishing TCM based on analytical equations and extracting model parameters becomes tedious. The model fitting capability for device outputs’ high-order derivatives is also limited. These drawbacks hinder fast and accurate device to circuit evaluation cycles. We develop a TCM based on multigradient neural network (MNN) using computational graph in the PyTorch framework. This MNN model is able to simultaneously capture the transistor dc/ac characteristics, such as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}-{V}/{Q}-{V}$ </tex-math></inline-formula> , their derivatives ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${G}-{V}/{C}-{V}$ </tex-math></inline-formula> ), and higher order derivatives accurately. Moreover, the model architecture can be widely adapted to various device types. Based on this model scheme, software is developed to enable the automated model generation for standard SPICE simulation. Finally, the model and software are validated for novel gate-all-around (GAA) Si cold source field-effect transistors (CSFET), and 19-stage ring oscillator and two-stage operational amplifier circuit simulations have also been demonstrated. This work reduces the cycle of novel device compact model creation and circuit benchmark simulation from months or weeks to hours. In addition, it enables more precise circuit simulation for analog and RF circuits, and it provides a rapid solution for early stage design technology cooptimization (DTCO).

A GaN-HEMT Compact Model Including Dynamic RDSon Effect for Power Electronics Converters

In order to model GaN-HEMT switching transients and determine power losses, a compact model including dynamic RDSon effect is proposed herein. The model includes mathematical equations to represent device static and capacitance-voltage characteristics, and a behavioural voltage source, which includes multiple RC units to represent different time constants for trapping and detrapping effect from 100 ns to 100 s range. All the required parameters in the model can be obtained by fitting method using a datasheet or experimental characterisation results. The model is then implemented into our developed virtual prototyping software, where the device compact model is co-simulated with a parasitic inductance physical model to obtain the switching waveform. As model order reduction is applied in our software to resolve physical model, the device switching current and voltage waveform can be obtained in the range of minutes. By comparison with experimental measurements, the model is validated to accurately represent device switching transients as well as their spectrum in frequency domain until 100 MHz. In terms of dynamic RDSon value, the mismatch between the model and experimental results is within 10% under different power converter operation conditions in terms of switching frequencies and duty cycles, so designers can use this model to accurately obtain GaN-HEMT power losses due to trapping and detrapping effects for power electronics converters.

Silicon Carbide Junction Field Effect Transistor Compact Model for Extreme Environment Integrated Circuit Design

Abstract Presented is a temperature and geometry scalable 800°C Silicon Carbide (SiC) Junction Field Effect Transistor (JFET) compact device model designed to simulate the small signal effects of the SiC JFET-R process developed by NASA Glenn Research Center. With the JFET-R process pushing the temperature limits of integrated circuits, a high-fidelity device model capable of predicting the performance over temperature and geometry is required to realize the thermal ruggedness this process provides. A high temperature (HT) packaging system was utilized to characterize a SiC JFET device up to 800°C with a dwell time of 9 hours during a single test. Invaluable device characterization data was obtained and utilized to extend the device model presented to simulate SiC JFET performance continuously over 800°C.

Re-Assessment of Steep-Slope Device Design From a Circuit-Level Perspective Using Novel Evaluation Criteria and Model-Less Method

Power is becoming a major bottleneck in energy constraint applications such as internet-of-things (IoT). Emerging steep-slope devices such as tunnel FETs (TFET) and negative capacitance (NC) FETs are promising candidates for such type of applications. Nevertheless, due to the time-consuming characterization process and inconsistent evaluation criteria, conventional co-design and co-optimization process between novel devices and logic circuits takes too much time and its results rarely meet expectation. As a result, conventional co-design and co-optimization are quite inefficient. In this paper, for the first time, a new criterion is utilized to evaluate novel steep-slope devices for ultra-low power applications. In addition, an efficient evaluation method is proposed, which not only quantitatively guides device design, but also evaluates devices from a circuit perspective without the need for device compact model and circuit simulation. From a device design perspective, optimal design metrics of novel steep slope devices such as average subthreshold slope (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Savg</sub> ), off current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ), and on current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) can be directly figured out with the help of the proposed evaluation criteria and method. From a circuit design perspective, the proposed evaluation criteria and method can be used to determine application scope.

A Process-Aware Memory Compact-Device Model Using Long-Short Term Memory

With the immense increase in the processing data during the scaling down of semiconductor devices by Moore's Law, it is in urgent need to use data analytics to meet the state of the art performance in both manufacturing and device compact modeling. In particular, managing the fabrication cost and promptly providing compact device models, especially for new or emerging devices, is challenging. To ease out these issues, we propose a unified, general-purpose, process-aware machine learning (ML) based compact model (CM) for resistive random-access memory (RRAM), and the same methodology can be used for any memory devices with hysteresis. A long short-term memory (LSTM) ML model is used to fit the RRAM current-voltage (I-V) characteristics. The memorizing capability of LSTM ensures one model can fit both RRAM low resistance state (LRS) and high resistance state (HRS). The fitted dataset is based on the fabricated RRAM samples using TaN/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Pt/Ti/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si structure. The resultant fitting error is 0.0096 in sinusoidal wave input voltage and 0.0148 in random walk voltage sequences. In the process-aware demonstration, we use post-oxide annealing dataset from 300°C to 500°C. The root mean squared error (RMSE) in the process-aware RRAM compact model is 0.0028. Thus, the LSTM-based CM has the potential to compete with the conventional compact device models in terms of shorter developing time, better fitting capability in emerging devices and a large number of devices, easily incorporated process-aware models, and one unified model accounting for LRS and HRS ensuring differentiability. We propose that the LSTM based memory CM can be useful in intelligent manufacturing, process tuning, and simulation program with integrated circuit emphasis (SPICE) modeling in circuit simulation.

Compact Modeling of High-Voltage Gallium Nitride Power Semiconductor Devices for Advanced Power Electronics Design

This work presents a physics-based compact GaN device model that can predict the performance characteristics of a wide range of GaN devices for power electronics applications. The model has been validated against the measured characteristics of a 650 V commercially available GaN device. The higher voltage range devices exhibit quasi-saturation on-state behavior due to drift resistance, which is evident from their on-state behavior. Also, higher voltage GaN devices have significant nonlinear capacitance characteristics due to the presence of field plates connected to the source and gate terminals. The field plates are fabricated to improve the electric-field distribution in the channel. The field plates result in significant nonlinearity in the channel capacitance that can be quantified as successive depletion in the device capacitances. The model accurately captures these phenomena in the dc and C-V device characteristics. The model also captures the third-quadrant behavior of all GaN devices with model parameters that are decoupled from the first quadrant while maintaining continuity between the first and third quadrants. Dynamic validation of the model is performed from the double-pulse test. The proposed model can be used to characterize commercially available high-voltage GaN devices that can be used in power electronic applications and design.

Neuroevolution-Based Efficient Field Effect Transistor Compact Device Models

Neuroevolution-Based Efficient Field Effect Transistor Compact Device Models

A predictive model for high-frequency operation of two-dimensional transistors from first-principles

First-principles-based device models are in demand in the semiconductor industry to assess the impact of new materials at very early phases of the technology development. Existing models for the 2D metal–oxide–semiconductor field-effect transistor work under quasi-static limit and can only be used for designing circuits operating under half of the transistor's intrinsic cut-off frequency. Here, we develop a compact device model for phosphorene-based transistor that takes into account its band structure anisotropy as well as the carrier inertia, which is crucial for high-frequency operation. In a multi-scale approach, density functional theory based calculation is first carried out to obtain the material specific parameters, which are then used to develop a continuity equation based non-quasi-static model to gain insight into the high-frequency behaviors. We find that channel orientation has a strong impact on both the low and high frequency conductances; however, it affects only the high-frequency component of capacitances. The model is then implemented in an industry-standard circuit simulator using relaxation-time-approximation technique and simulations are conducted to demonstrate its applicability for near cut-off frequency circuit operation. The proposed modeling methodology, which connects material to circuit, thus helps us to expand the design space, where technology downscaling could be very challenging and expensive.

Statistical Extraction of Normally and Lognormally Distributed Model Parameters for Power MOSFETs

In this paper, we propose a new statistical model parameter extraction method for compact power device models. While existing parameter extraction methods are only applicable for the parameters that follow normal distributions, the proposed method can simultaneously incorporate the model parameters that follow lognormal distributions. In addition, a set of dominant model parameters, which largely contributes to the characteristic variation of power MOSFETs, has been studied on the basis of the proposed statistical parameter modeling. Through the numerical analysis upon measured drain currents of planar and trench SiC power MOSFETs, we demonstrate that the fluctuation of the current characteristics can be represented by a small number of dominant parameters. In our example, threshold voltage and current scaling factor are identified to be particularly important to approximate the fluctuation of the current characteristics in both structures.

An Automated Model Tuning Procedure for Optimizing Prediction of Transient and Dispersive Behavior in Wide Bandgap Semiconductor FETs

This article presents an automated procedure for developing wide bandgap semiconductor device models capable of capturing high-frequency effects in applications relevant to next generation power electronics. A derivative-free global optimization algorithm is used to autonomously model both the static and dynamic behavior of a power semiconductor device. This procedure is demonstrated with a specific model, but the procedure is model-agnostic and not exclusive to this implementation. The modeling procedure creates a compact and modular power electronic device model accounting for both frequency-dependence of device inter-electrode capacitances and characterization uncertainty of device parasitic package inductances. The procedure targets prediction of specific signal features in the transient device behavior. Digital twin development and validation are performed under disparate switching conditions to demonstrate the overall improvement in model predictive power. The proposed modeling approach serves to reduce manual model development time, while improving time-domain prediction under switching conditions of interest to application engineers and systems integrators. This is particularly important in the case of wide bandgap semiconductors, which pose challenges for conventional device models due to their fast switching dynamics. The effectiveness of the presented method is demonstrated by automatically generating a device model for a 1.2-kV SiC mosfet and comparing predicted switching behavior with empirical double pulse test behavior.

Compact device modelling of interface trap charges with quantum capacitance in MoS2-based field-effect transistors

An effective way to obtain interface trap density in transition metal dichalcogenide field-effect transistors (FETs) via compact device modelling is presented in this study. A computationally efficient model is utilised to evaluate the interface trap charges in a MoS2-based FET device. This model improves the accuracy of the computed surface potential, which is affected by trap charges. The existence of trap states on the interface level can be confirmed by studying the capacitance versus gate voltage () relationship. Most of the previously proposed models ignore the effect of the quantum capacitance when predicting the electrical performance of MoS2-FETs. The electrical performance of a metal-oxide-semiconductor FET with a two-dimensional (2D) molybdenum disulphide (MoS2) channel that introduces a quantum capacitance by including a gate is evaluated. The gate quantum capacitance in parallel with the interface trap capacitance is a second capacitance in series with the gate oxide capacitance and MoS2 capacitance This research explores the process of evaluating the interface trap density from published experimental data of MoS2-based FETs. Using the evaluated trap density values, the device parameters are calculated by considering the relative permittivity of the dielectric hafnium oxide (HfO2) layer, surface potential, interface trap charge and interface trap capacitance Finally, the calculated and experimental data are compared through the normalised root-mean-square deviations (RMSD) to validate the accuracy of the model.

Advances in Compact Modeling of Organic Field-Effect Transistors

In this review, recent advances in compact modeling of organic field-effect transistors (OFETs) are presented. Despite the inherent strength for printed flexible electronics and the extremely aggressive research conducted over more than three decades, the OFET technology still seems to remain at a relatively low technological readiness level. Among various possible reasons for that, the lack of a standard compact model, which effectively bridges the device- and system-level development, is clearly one of the most critical issues. This article broadly discusses the essential requirements, up-to-date progresses, and imminent challenges for the OFET compact device modeling toward a universal, physically valid, and applicable description of this fast-developing technology.