Abstract
Neuroevolution-Based Efficient Field Effect Transistor Compact Device Models
Highlights
Metal Oxide Semiconductor (MOS) is the most widely used semiconductor device in integrated circuits (IC) due to its superior electrical properties
Device compact modeling is achieved by following complex physics and equations, which highly depend on each material layer and its interfaces, traps, and doping profile [1,2,3]
Stochastic gradient descent (SGD) or other gradient-based algorithms [15,16,17] have proved to be most effective in the optimization of largescale deep neural network-based supervised learning models to update the network weights and biases
Summary
Metal Oxide Semiconductor (MOS) is the most widely used semiconductor device in integrated circuits (IC) due to its superior electrical properties. Stochastic gradient descent (SGD) or other gradient-based algorithms [15,16,17] have proved to be most effective in the optimization of largescale deep neural network-based supervised learning models to update the network weights and biases. Most of the previous works in semiconductor device compact models are based on dense connections using MLP[4, 6, 7]. Neuroevolution (NE) [18,19,20,21], a highly effective evolutionary algorithm (EA), uses GA for the evolution of network architecture or topology. In RL, where the model learns by trial and error to try different action sequences to maximize the reward [22], the ability of NE to evolve the neural network topology along with weights has made them outperform baseline RL benchmark tasks [23, 24]. Some of the results in this work can be found in a student thesis [41]
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