Common-gate Transistor Research Articles

A 0.064 mm2 16-Channel In-Pixel Neural Front End with Improved System Common-Mode Rejection Exploiting a Current-Mode Summing Approach

In this work, we introduce the design of a 16-channel in-pixel neural analog front end that employs a current-based summing approach to establish a common-mode feedback loop. The primary aim of this novel structure is to enhance both the system common-mode rejection ratio (SCMRR) and the common-mode interference (CMI) range. Compared to more conventional designs, the proposed front end utilizes DC-coupled inverter-based main amplifiers, which significantly reduce the occupied on-chip area. Additionally, the current-based implementation of the CMFB loop obviates the need for voltage buffers, replacing them with simple common-gate transistors, which, in turn, decreases both area occupancy and power consumption. The proposed architecture is further examined from an analytical standpoint, providing a comprehensive evaluation through design equations of its performance in terms of gain, common-mode rejection, and noise power. A 50 μm × 65 μm compact layout of the pixel amplifiers that make up the recording channels of the front end was designed using a 180 nm CMOS process. Simulations conducted in Cadence Virtuoso reveal an SCMRR of 80.5 dB and a PSRR of 72.58 dB, with a differential gain of 44 dB and a bandwidth that fully encompasses the frequency range of the bio-signals that can be theoretically captured by the neural probe. The noise integrated in the range between 1 Hz and 7.5 kHz results in an input-referred noise (IRN) of 4.04 μVrms. Power consumption is also tested, with a measured value of 3.77 μW per channel, corresponding to an overall consumption of about 60 μW. To test its robustness with respect to PVT and mismatch variations, the front end is evaluated through extensive parametric simulations and Monte Carlo simulations, revealing favorable results.

A broadband single-ended active-feedforward -noise-canceling LNA with IP2 enhancement in stacked n/pMOS configurations

In this paper, we present a broadband low-noise amplifier (LNA), using active-feedforward noise-cancellation and complementary n/pMOS configurations. Based on traditional common-gate (CG) and common-source (CS) noise canceling topology, the applied active feedforward stage reduces the CG's dc current and alleviates its resistive load tradeoff between noise and headroom. Meanwhile, the active feedforward stage follows the same noise cancellation (NC) principle as the CG transistors. A low noise figure is thus obtained. In addition, the complementary n/pMOS configuration is used to cancel second-order distortions and double current efficiency. Two π-type matching networks are utilized to broaden the bandwidth of S11 and gain. After applying these techniques, an LNA prototype was designed in standard 65 nm CMOS technology. Simulation results display a gain of 14–17 dB and a noise figure (NF) of 2.45–3.45 dB within a bandwidth of 1–12 GHz. The linearity of IIP3 and IIP2 are −2.4 and 23 dBm at 5 GHz. The presented circuit consumes only 7.8 mW of dc power while occupying an area of 0.21 mm2.

Comparison of single event effect on cascoded low noise amplifier performance metrics for two different frequencies

This manuscript examines the impact of single event effects (SEEs) on the well-known cascoded low noise amplifier (LNA) topology connected with an inter-stage inductor sandwiched between the common source (CS) and common gate transistors for boosting the LNA parameters (i.e., gain, etc). In this article, we have considered that the LNA operates at two different frequencies, such as 10 and 30 GHz, in a radiation-prone environment. The effect of SEEs is analyzed in two ways: (i) non-applying a RF input with dc voltage only, and (ii) applying a RF input with dc bias voltage. The first analysis uses basic integration to evaluate the collected charge (QCollected) for a drain terminal momentary current spike with a suitable time period, and the second analysis estimates the LNA output discontinuity (distortion) using a spectrogram (short-time FFT) to determine the radiation strikes on the cascoded LNA. The collected charge is calculated in the temporal analysis, and the discontinuity of LNA’s RF output is analysed using the spectrogram in the frequency domain analysis. From the temporal and frequency analysis, the LNA that operates at a lower frequency (10 GHz) provides more discontinuity in LNA output (causing more disturbance) than the LNA that operates at a higher frequency (30 GHz).

Quad path, CG-CS resistive feedback LNA architecture for 25–35 GHz band

In this paper, a Quad Path Noise Cancellation (QPNC) Low Noise Amplifier (LNA)presented for 5G sub-band 25-35GHz using GPDK 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology; which is composed of Common Source (CS) & Common Gate (CG) stages with resistive feedback and current reuse at the output. QPNC is used to cancel the noise of common gate transistors, which leads to reduce the noise fig. (NF). Resistive feedback is used to tradeoff between the input matching, gain, and NF i.e. overall refining the Figure of Merit (FoM) of the circuit. Mathematical analysis of impedance matching, gain, noise transfer function, and NF have been done using the small signal model of QPNC-LNA. Simulation has been done on Cadence Virtuoso software using GPDK 45 nm CMOS technology. Pre layout simulation result shows the minimum value of gain is 13.38 dB at 30.9GHz while the maximum value is 14.12 dB at 25.87GHz and flat over the entire frequency range. S11 i.e. input reflection coefficient is ranging from −16.16 dB at 25.21GHz to −11.52 dB at 35GHz for 50 Ω input impedance matching. NF value ranges from 2.69 dB at 25.69GHz to 3.77 dB at 35GHz. The IIP3 value for the proposed QPNC-LNA is 5.3 dB. For the four corners SS, SF, FS, and FF, process corner simulation has been performed. Post-layout simulation results depict the maximum value of gain is 12.71 dB at 25.75GHz. NF value is varying from 2.88 dB to 4.02 dB while the input reflection coefficient is ranging from −10.12 dB to −14.13 dB for 10GHz bandwidth. The circuit consumes 17.53 mW power at 1.2 V under a DC current of 14.61 mA, FoM1 is 8.36 dB and FoM2 of the proposed LNA is 49.35 dB. The layout of the proposed LNA is having an area of 0.03026mm2.

DC-10 GHz broadband linear power amplifier for 5G applications using 180 nm CMOS technology

This article suggests a broadband linear power amplifier (PA) for DC-10 GHz for Fifth-generation (5G) and multi-standard applications using 180 nm CMOS technology. The suggested radio frequency power amplifier is appropriate for wideband LTE, IoT, WSN, multi-standard, and 5G radio frequency transmitters. T-coil peaking and bridged-shunt-series peaking amplifiers are used for bandwidth extension and gain flatness. Also, the interstage matching inductors between common source and common gate transistors are applied to improve radio frequency achievement. The suggested PA consists of four stages as follows; input stage, two stages using the T-coil peaking technique, and the last stage utilizing bridged-shunt-series peaking topology. The input stage is a complementary current reuse (CCR) common gate with active shunt feedback (SFB) architecture. It is utilized to extend the matching of RF input impedance with agreeable linearity and power gain at little power consumption. The second stage works in class-C operation to enhance the efficiency and reduce DC power consumed whereas the class-AB mode is utilized in the third and fourth stages to improve the output power. The suggested PA obtains a peak constant power equal to 14.25 dBm, a maximum Power-Added-Efficiency (PAE) of 16 %, and a peak gain equal to 22 dB. The proposed power amplifier dissipates a DC power of 80 mW. The die size of the proposed power amplifier equals 1mm2, whereas the total chip size includes the pads is 1.62mm2.

Design and Analysis of a Cascode Distributed LNA With Gain and Noise Improvement in 0.15-μm GaAs pHEMT Technology

This brief presents a 2.0~42.0 GHz ultra-wide bandwidth Cascode distributed low-noise amplifier (CDLNA) MMIC design. With the proposed coupled-line (CL) sections between each drain-artificial transmission line (D-ATML) node and related gate-artificial transmission line (G-ATML) node, the traveling signal is reused to enhance the gain and broaden the operation bandwidth simultaneously. To improve the gain further, the inductive gain peaking has also been employed at each drain of common-source (CS) and common-gate (CG) transistors. Meanwhile, an active termination technique incorporating active and passive elements has been adopted to achieve better noise figure (NF) performance. Employing the proposed techniques, an LNA prototype has been designed and fabricated in a 0.15- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaAs E-Mode pHEMT technology with the chip size of 1.53 mm2 including all the pads. From test results, the proposed CDLNA demonstrates a peak gain of 14.1 dB, the best NF of 2.1 dB, a group delay of 102 ± 58.4 ps, and 23.25/14.7 dBm best OIP3/OP1dB, respectively. The total power consumption is 129 mW under 3 V VDD.

28-GHz Dual-Mode Phase-Invariant Variable-Gain Amplifier With Phase Compensators

A 28 GHz dual-mode phase-invariant wide-dynamic-range variable-gain amplifier (VGA) with adaptive phase compensators is presented for use as a gain control element in a beamforming IC, which must have a small chip size and low power consumption. It consists of a single-stage differential amplifier with main and auxiliary signal paths, where the auxiliary paths are introduced to achieve most-significant-bit (MSB) gain control. The wide-gain dynamic range is also covered through a least-significant-bit (LSB) gain-control scheme, which is implemented with bias control of common gate (CG) transistors in the main signal paths. In addition, the phase variations due to the gain controls are drastically reduced by introducing phase compensators for both gain controls. The proposed VGA shows a gain dynamic range of 24 dB, maximum gain of 13 dB and root-mean-square (RMS) phase error of 2.77 degrees at 28 GHz. The maximum DC power consumption is 24 mW at the maximum gain, the minimum is 4 mW at the minimum gain, and the chip size is 0.066 mm2.

A Low-Phase Error Cascode CMOS Variable Gain Amplifier With 180° Phase Control for Phase Array Systems

A comprehensive analysis is derived to understand the mechanism of phase errors in cascode CMOS variable gain amplifiers (VGAs). According to the analysis, source–drain parasitic capacitors ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {ds}}$ </tex-math></inline-formula> ) of common gate (CG) transistors in off-region are the main causes for phase errors. An independent cascode current canceling (ICCC) VGA is proposed to relax phase errors by minimizing the effect of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {ds}}$ </tex-math></inline-formula> within a broadband. The proposed VGA achieves a 16-dB gain control with a 1.6° phase error and a 0.2-dB gain error from 15 to 25 GHz by 40-nm CMOS technology. Owing to the cascode structure, the peak gain of the VGA is 12 dB with only one stage including input–output pads consuming 16-mW power from 1.1-V voltage. Besides, the VGA can also serve as a 180° phase shifter (PS) due to ICCC structure with a 1.5° phase error and a 0.2-dB gain error from 15 to 25 GHz. The measured −3-dB bandwidth is 5 GHz, and output 1-dB compression point (OP1dB) is over 2.5 dBm in the maximum gain state. The core area is 0.065 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> excluding input–output pads.

A Simulated Study of 65 nm CMOS 2GHz Front-End Preamplifier Circuit for Optical Fiber Applications

In this research a new design of the transimpedance amplifier (TIA) with the current mirror was employed by the technique (65nm). The TIA consists of a common gate transistor amplifier (CG TIA) and a common source amplifier as an input stage with local active feedback with a second stage of a current mirror and local active feedback to increase gain. In order to verify the performance of the proposed TIA, a circuit simulation was carried out in the LT spice program using coefficients with the technique (65nm CMOS). The simulation results indicate that the interfacial impedance gain is (41 dBΩ) at a bandwidth frequency of (2.0 GHz-3dB) for an input capacitor of (100 fF) and an input referred noise current spectral density of (14 pA/√Hz) and a power consumption value of (0.091 mw) at an applied voltage (1V). The main focus of this research is low consumption of power and voltage compared to another research.

Design and Analysis of High-Gain and Compact Single-Input Differential-Output Low Noise Amplifier for 5G Applications

This letter describes the design, analysis, and testing of a 28-GHz single-input differential-output (SIDO) low-noise amplifier (LNA) with a noise figure of 2.5 dB, compact size (0.25 mm²), and high gain (22.3 dB). The proposed LNA was fabricated using the Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS process. This amplifier contains a two-stage common-source (CS) buffer amplifier for a low-noise design and combines CS and common-gate transistors for converting single-ended signal into differential signal. A novel method of common-mode rejection ratio optimization is used to determine the optimal phase compensation transmission line and transistor size to reduce gain and phase imbalances simultaneously. The gain and phase imbalances were 0.042 dB and 2.6° at 28 GHz, respectively. Compared with published LNAs, this SIDO LNA achieved the high figure of merits (FoMs) of 7.17 and 2.27, respectively. Therefore, this LNA can be used for 5G NR band of n257 (26.5-29.5 GHz), n258 (24.25-27.5 GHz), and n261 (27.5-28.35 GHz).

A 0.96-mW dB-Linear Variable Gain Amplifier With 0.4-dB Linearity Error Over a 62.4-dB Gain Tuning Range

This letter presents a low-power dB-linear variable gain amplifier (VGA) with a small linear-in-dB error over a wide gain tuning range. An exponential current ratio is realized in the linear-in-dB control circuit based on the subthreshold I-V characteristic. The VGA is built with subthreshold common-gate transistors as current steering, accurately replicating the exponential current ratio and forming a tunable gain. Implemented in 55-nm CMOS technology, the proposed VGA occupies a compact active area of 0.011 mm2 excluding the buffer. It achieves a linear-in-dB error of 0.4 dB over a gain tuning range of 62.4 dB, corresponding to the state-of-the-art relative error of 0.6%. The proposed design shows constant 80-MHz bandwidth with a power consumption of 0.96-mW.

매칭된 캐스코드 전력 셀 기반 K-/Ka-대역 CMOS 전력 증폭기

This study proposes a K-/Ka-band CMOS power amplifier (PA) with a matched cascode power cell. Interstage inductors are introduced between the common source (CS) and common gate (CG) transistors to achieve high power gain and high reverse isolation of the PA. Cold FETs are configured with interstage inductors to reduce the phase distortion of the PA. The input and output matching networks of the PA are designed as broadside-coupled transformers to obtain a high coupling coefficient and low insertion loss. The proposed PA is fabricated using a 65 nm RF CMOS process, whose chip dimensions are 0.99 mm × 0.57 mm. The device achieves a saturated output power of 19~21 dBm, power-added efficiency of 32~37 %, and power gain of 6.7~7.7 dB in a frequency range of 24~28 GHz. The linear power values for the IMD &lt; −30 dBc are in the range of 12.5~15 dBm in a frequency range of 24~28 GHz.

A 3.6 mW 60 GHz Low-Noise Amplifier With 0.6 ns Settling Time for Duty-Cycled Receivers

This letter presents the first duty-cycled low-noise amplifier (LNA) operating in the V-band (40-75 GHz). The amplifier employs a two-stage cascode topology and focuses on low power consumption and therefore fast settling times. The switching is achieved by using inverters at the common-gate (CG) transistor of the cascode stage. This control technique enables adapting the duty-cycle and, therefore, the data rate depending on the required performance. The LNA can be operated in an oversampling mode fulfilling a wake-up function and consuming only 22 μW for a data rate of 294 kb/s or in continuous mode dissipating 3.6 mW. A settling time of 0.6 ns, a rise time of 19 ps, and a fall time of 27 ps have been experimentally demonstrated on a prototype fabricated in a 22 nm fully-depleted silicon-on-insulator (FD-SOI) technology. The measurement results include a peak gain of 18 dB, a 3-dB bandwidth of 18 GHz, an average noise figure (NF) of 4.9 dB within the 3-dB band, and an input 1 dB compression point (P1dB) at 60 GHz of -21.1 dBm.

A 28-GHz CMOS Power Amplifier Linearized by Dynamic Conductance Control and Body Carrier Injection

A 28-GHz linear CMOS cascode power amplifier (PA) that adopts two types of analog linearization methods, dynamic conductance control (DCC) and body carrier injection (BCI), is presented here. The former method controls the load conductance of a common-source (CS) amplifier according to the input power of the PA. This improves the AM-AM and AM-PM characteristics of the cascode PA, which is also analyzed with an equivalent circuit model. The latter injects the carrier signal into the body of a common-gate (CG) transistor, which increases the voltage headroom of the CS transistor. This improves the AM-AM of the cascode PA and also helps to stabilize the PA by reducing the drain-source capacitance of the CG transistor. The proposed PA is fabricated in a 65-nm CMOS process and shows a gain of 15.9 dB, an output 1-dB compression point of 17.7 dBm, and a saturation output power of 19.1 dBm with a peak power-added efficiency (PAE) of 41.2% at 28 GHz.

A K-Band Dual-Mode Common Gate Cross-Summing VG-LNA With Low Phase Variation

This brief presents a variable-gain low-noise amplifier (VG-LNA) with a common gate (CG) cross-summing configuration, which is fabricated using a 65-nm RF CMOS process. It has a wide gain control range as well as a high input 1 dB gain compression point (IP1dB) at high-gain by introducing a split common-gate transistor (SCGT) technique. In addition, output phase compensation is achieved by adopting a tuning capacitor at the cascode node. This LNA is designed as 2-stage cascode, and the area excluding the pad is 0.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It consumes 25.2 mW with a 1.2-V power supply. It shows a gain of 25 dB and a noise figure of 3.4 dB at 22 GHz. The measured minimum IP1dB is -27.5 dBm, and the root-mean-square phase error is 0.34° over the gain control range of 14 dB at 22 GHz.

A 21-to-41-GHz High-Gain Low Noise Amplifier With Triple-Coupled Technique for Multiband Wireless Applications

This brief presents a wideband millimeter-wave (mm-Wave) low noise amplifier (LNA) with a triple-coupled technique for multiband wireless applications. To enlarge the gain and reduce the supply voltage, a modified cascode topology exploiting a triple-coupled transformer is developed. Thanks to the transformer, the transconductance of the common-gate (CG) transistor of the cascode topology is also effectively boosted, and hence the gain is further increased. Furthermore, high-order networks, which are realized by combinations of π- and T/L-type structures or transformers, are employed to implement the input, inter-stage, and output impedance matchings. They significantly broaden the bandwidth of the circuit. The LNA is demonstrated using a commercial 65-nm CMOS process. The measurement results show that the circuit achieves a maximum gain of 28.5 dB and a 3-dB gain bandwidth of 20 GHz with 32-mW dc power consumption ( P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> ). The measured noise figure (NF) and input 1-dB gain compression point ( IP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> ) are 2.7~3.2 dB and -24.6~-20.4 dBm, respectively, over the entire operating bandwidth.

An inductor-less CMOS broadband balun gm-boosting LNA exploiting noise cancellation techniques

This paper presents a 100 MHz to 6 GHz broadband inductor-less single-to-differential balun gm-boosting low-noise amplifier (LNA) for multi-standard radio applications. Two mechanisms of noise cancellation techniques have been innovatively introduced in this work. To achieve the wideband input matching, high gain, and low noise figure simultaneously, a feed-forward thermal noise cancellation technique has been exploited in the design of the inverting amplifier for transconductance enhancement. Moreover, the balanced balun operation transforms the thermal noise of the common-gate transistor into a common-mode signal, and cancels it at the LNA’s differential outputs. The proposed design has been fabricated in a standard 0.18-um RF CMOS technology and occupies a die area of 0.04 mm2. Measurement results have shown that it has achieved a good performance over the whole operation frequency range of interest (100 MHz to 6 GHz) with a gain of 15.5 dB, IIP3 of 1.5 dBm, minimum NF of 3.0 dB and current dissipation of 8 mA at 1.8 V supply voltage.

A 5.7 mW, UWB LNA for Wireless Applications Using Noise Canceling Technique in 90 nm CMOS

AbstractA 3–12 GHz ultra-wideband (UWB) low noise amplifier (LNA) is proposed in this paper. The first stage common-gate (CG), common-source (CS) noise canceling approach is used to achieve low noise-figure (NF). CG configuration at the input stage provides wideband input-matching. The noise of CG transistor is cancelled by systematically added two parallel CS transistors, whose outputs are cascoded in second stage. In order to achieve flat power gain (S21) response, a series peaking inductor is used in the second stage. The proposed LNA is designed in 90 nm CMOS process with chip-layout area of 0.467 mm2 and in comparison to the existing LNAs, it consumes a low power of 5.7 mW from a 1 V supply. The achieved input-reflection coefficient (S11) is &lt;−7.5 dB, output-reflection coefficient (S22) is &lt;−7.6 dB with NF &lt; 5.8 dB for 3–12 GHz UWB and third-order intercept point (IIP3) of −19 dBm. It achieves high and flat S21 of 20.84 ± 0.28 dB over 4.2–10 GHz, with NF ranging from 2.6–3.6 dB.

Balun LNA Thermal Noise Analysis and Balancing With Common-Source Degeneration Resistor

The Balun low noise amplifier (LNA) is an LNA that exploits a combination of a common-source (CS) and a common-gate (CG) transistors, which cancels the noise and distortion of the CG stage. And since the CG is known to be linear, only the CS needs to be carefully designed and optimized. The Balun LNA also cancels the distortion and noise of the CG. In this paper, the CS section will be fully analyzed, and shown how the condition set in the literature review still satisfy the balancing output and cancel the CS stage thermal noise as well as the CG thermal noise. Also, forward body biasing (FBB) is used to reduce the threshold voltage and an addition of CS degeneration resistor to balance the output while still canceling the thermal noise of the transistors is tested using UMC180nm on Cadence. The LNA achieves a gain of 19-16dB, NF < 3.6 over the bandwidth 200M-1.9GHz without a CS degeneration. A 17.8-14.8dB gain, a NF < 3.8 over the bandwidth 200MHz-2.1GHz and power consumption of 12mW in both cases. Although outside the bandwidth, at ISM 2.4GHz a gain of 14.5dB and a NF of 3.8 is achieved, making it suitable for wireless sensor node (WSN) applications. According to the author’s knowledge, this is the first time the degeneration resistor noise analysis on a Balun LNA is derived and analyzed.

A 0.096-mm$^{2}~1$ –20-GHz Triple-Path Noise- Canceling Common-Gate Common-Source LNA With Dual Complementary pMOS–nMOS Configuration

This article proposes a novel wideband common-gate (CG) common-source (CS) low-noise amplifier (LNA) with a dual complementary pMOS–nMOS configuration to provide a current-reuse output. Triple-path noise-cancellation is effectively revealed to eliminate the thermal noise of the two CG transistors. Simultaneously, partial cancellation of intrinsic third-order distortion of output-stage transistors improves the input third-order intercept point (IIP3). In addition, we embed a resistive feedback in one of the auxiliary CS amplifiers to balance the multiple tradeoffs between noise figure (NF), input matching (S11), and forward gain (S21). Fabricated in 65-nm CMOS, the proposed wideband LNA exhibits an IIP3 of 2.2–6.8 dBm and an NF of 3.3–5.3 dB across a 19-GHz BW while consuming 20.3 mW at 1.6 V. S11 is $\pi $ -type input-matching network. The LNA exhibits a peak $\text{S}_{\vphantom {D_{j}}21}$ of 12.8 dB and occupies a very compact die area of 0.096 mm2.