A 3.6 mW 60 GHz Low-Noise Amplifier With 0.6 ns Settling Time for Duty-Cycled Receivers

Abstract

This letter presents the first duty-cycled low-noise amplifier (LNA) operating in the V-band (40-75 GHz). The amplifier employs a two-stage cascode topology and focuses on low power consumption and therefore fast settling times. The switching is achieved by using inverters at the common-gate (CG) transistor of the cascode stage. This control technique enables adapting the duty-cycle and, therefore, the data rate depending on the required performance. The LNA can be operated in an oversampling mode fulfilling a wake-up function and consuming only 22 μW for a data rate of 294 kb/s or in continuous mode dissipating 3.6 mW. A settling time of 0.6 ns, a rise time of 19 ps, and a fall time of 27 ps have been experimentally demonstrated on a prototype fabricated in a 22 nm fully-depleted silicon-on-insulator (FD-SOI) technology. The measurement results include a peak gain of 18 dB, a 3-dB bandwidth of 18 GHz, an average noise figure (NF) of 4.9 dB within the 3-dB band, and an input 1 dB compression point (P1dB) at 60 GHz of -21.1 dBm.