Common Drain Configuration Research Articles

Design of a low power LNA circuit with noise canceling approach in 90 nm CMOS process

In this manuscript, a low noise amplifier (LNA) circuit with low power consumption of 5.3 mW for 3–12 GHz ultra-wideband (UWB) is designed in 90 nm standard CMOS process. A noise-canceling (NC) approach consisting of both common-gate (CG) and common-source (CS) as input stage, followed by the gm-boosted current-reused stage to enhance the gain performance, is used in the proposed design. After noise-canceling, the achieved noise-figure (NF) is ranging from 2.28 to 3.55 dB for 3.1–10.6 GHz and a maximum of 4.0 dB at 12 GHz. Input-reflection coefficient (S11) of < −12.57 dB is achieved from this CG-CS input-matching stage. With the use of parallel-series LC matching with series-peaking-inductor followed by the gm-boosting stage improves the gain-bandwidth and delivers a flat power-gain (S21) of 18.33 ± 0.76 dB over 3–12 GHz. The CG configuration at the input side provides a high reverse-isolation (S12) of less than −78.23 dB and common-drain configuration with NMOS load at the output side ensures less than −11.79 dB output-reflection coefficient (S22) over the proposed frequency range. The proposed LNA is operated with 0.7 V Vdd and the achieved intercept points for input (IIP3) and output (OIP3) are −11.1 dBm and +6.2 dBm, respectively.

Low-Voltage LDO Regulator Based on Native MOS Transistor with Improved PSR and Fast Response

In this paper, a low-voltage low-dropout analog regulator (ALDO) based on a native n-channel MOS transistor is proposed. Application of the native transistor with the threshold voltage close to zero allows elimination of the charge pump in low-voltage regulators using the pass element in a common drain configuration. Such a native pass transistor configuration allows simplification of regulator design and improved performance, with supply voltages below 1 V, compared to commonly used regulators with p-channel MOS transistors. In the presented design of ALDO regulator in 180 nm CMOS X-FAB technology, an output voltage of 0.7 V was achieved with an output current of 10 mA and a supply voltage of 0.8 V. Simulation results show that despite the low supply voltage, output voltage spikes do not exceed 70 mV at the worst technology corner when output current transients from 100 µA to 10 mA. Under such conditions, stable operation and power supply rejection PSR = 35 dB were achieved with an output capacitance of 0–500 pF. The proposed regulator allows to push the limit of ALDO regulator applications to voltages below 1 V with only slight degradation of its performance.

New Measurement Method for Self-Heating in Silicon-on-Insulator MOSFETs Based on Shared Series Resistance

A new method using temperature dependent shared series resistance in a pair of devices with common drain configuration is proposed to measure self-heating (SH) in advanced MOSFETs. The proposed measurement technique depends on the intrinsic series resistance and is not limited to the spatial proximity between the heater and the sensor. The developed method demonstrated on the silicon-on-insulator (SOI) MOSFETs reveals that the more accurate SH assessment can be obtained compared to other methods that are sensitive to the distance from heat source. Furthermore, the extraction of intrinsic series resistance allows to quantify the process-induced variability of the contact resistance.

High performance active image sensor pixel design with circular structure oxide TFT

We report a high-performance active image sensor pixel design by utilizing amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with a circular structure. The TFT, configured with the inner electrode as source and outer electrode as drain, typically exhibits good saturation electrical characteristics, where the device has a constant drive current despite variations in drain voltage. Due to the very high output resistance exhibited by this asymmetric TFT structure with a circular shape, the pixel circuit considered here in common-drain configuration provides a higher gain of operation than a pixel circuit implemented with rectangular a-IGZO TFTs. They can be used as driving TFTs in active image sensor circuits. They are, therefore, good candidates for digital X-ray detectors in applications such as medical diagnostic procedures.

149. SELF-HEATING EFFECTS IN SILICON NANOSCALE MOSFET

Abstract: In this work we present a novel multiscale simulation approach that combines circuit level with device level simulations together with experimental measurements to uncover the temperature of the hot-spot at nanoscale MOSFET devices. The circuit level simulation is performed with COMSOL simulation software. This allows one to perform electro-thermal modeling given the input Joule heating terms, the magnitude and the location of which is determined with more physically-based electro-thermal Monte Carlo device simulator. Simulation results obtained with this simulator are in agreement with experimental measurements from IMEC using specialized heater-sensor test structures in common-source and common-drain configurations.

SELF-HEATING EFFECTS IN SILICON NANOSCALE MOSFET(A MULTISCALE MODELING APPROACH)

In this work we present a novel multiscale simulation approach that combines circuit level with device level simulations together with experimental measurements to uncover the temperature of the hot-spot at nanoscale MOSFET devices. The circuit level simulation is performed with COMSOL simulation software. This allows one to perform electro-thermal modeling given the input Joule heating terms, the magnitude and the location of which is determined with more physically-based electro-thermal Monte Carlo device simulator. Simulation results obtained with this simulator are in agreement with experimental measurements from IMEC using specialized heater-sensor test structures in common-source and common-drain configurations.

A +12-dBm OIP3 60-GHz RF Downconversion Mixer With an Output-Matching, Noise- and Distortion-Canceling Active Balun for 5G Applications

A CMOS millimeter-wave (mmWave) downconversion mixer with a local-oscillator (LO) buffer is proposed for wireless Gb/s data-transfer enabling systems, such as 5G systems. To obtain high linearity at low supply voltages, the proposed mmWave downconversion mixer adopts an on-chip transformer-based topology. In order to achieve differential to single-ended conversion and IF output matching, while maintaining a high linearity performance, the proposed mmWave downconversion mixer incorporates an active balun with common-source and common-drain configurations employing common-mode noise and third-order intermodulation distortion cancellations. The proposed downconversion mixer with active balun and LO buffer was implemented using a 65-nm CMOS process and it draws 18 mA from a 1 V supply voltage. It demonstrates a gain greater than 5.6 dB, noise figure less than 10.9 dB, and third-order output intercept point more than 12.4 dBm, in the band from 57 to 66 GHz.

Bias-Point Calculation and Parameter Extraction Using EKV Compact MOS Model Equation

ABSTRACTThe main aim of this tutorial is to apprise readers about parameter extraction and bias-point calculation using Enz–Krummenacher–Vittoz compact metal oxide semiconductor (MOS) model equation. The model equation has been applied to an NMOS (N-channel metal oxide semiconductor) transistor case present on the P-substrate and P-well. Two cases are considered to show parameters extraction and bias-point calculation for a modified/unmodified value of the transistor threshold voltage. After presenting equation simplification for the two cases, different parameter extraction methods are discussed. Then a common drain configuration biased by a resistance is simulated to match by hand-calculated results.

Multi-Scale Modeling of Self Heating Effects on Power Consumption in Silicon CMOS Devices

This work pursues a multi-scale modeling approach to combine interconnect and device level simulation in order to study the effects of carrier self-heating and thermal transport on device performance. More specifically, this work will focus on power consumption and heat dissipation in silicon CMOS technology. As device dimensions decrease to the nanometer scale, current density in the device active regions and the circuit interconnects increases [4]. This increase in current density leads to substantial increases in operating temperatures in critical regions of nano-scale electronic devices. We have already shown these effects in n-channel MOSFETs [2], and will continue to explore how this phenomenon affects p-channel MOSFETs and CMOS circuits. This paper presents the methodology used for the study, multi-scale results from the n-channel MOSFET simulations, and preliminary results from the device level p-channel MOSFET simulation. The modeling approach combines an electro-thermal device simulation with a thermal transport solver at the circuit level. The electrical simulation solves Poisson's equations self-consistently coupled with an ensemble Monte Carlo to determine internal electric fields and model electron and hole transport in the device [3]. The thermal simulation solves the energy balance equations for acoustic and optical phonons and uses the phonon energy to determine the lattice temperature [5]. The electro-thermal solver couples these two processes by introducing temperature dependent scattering to the carrier transport solver. Thermal transport can be modeled in a variety of ways: phonon Monte Carlo simulations are necessary for modeling extreme nano-scale and hot-carrier devices, energy balance modeling is used in this study to model thermal transport at the device level, and the Joule heating method commonly used in commercial device simulators is used in this study to model thermal transport at the interconnect level. The thermal modeling in the device and the interconnects is coupled using the device structure itself as an interface: the electro-thermal simulator provides Joule heating terms throughout the device to be used in the Joule heating simulator which in turn gives the temperature profile in the interconnects to be used as a boundary condition in the electro-thermal solver. These simulations are repeated in a self-consistent loop until convergence is achieved [2]. This modeling approach has been successfully applied to n-channel MOSFET devices and the results have been confirmed using a novel experimental approach. Two identical MOSEFTs in either common source or common drain configuration can be biased such that one device is in saturation and one device is in cut-off or sub-threshold region. The device in saturation heats up and the device in sub-threshold is used as a sensor; the temperature in the sensor can be determined using the subthreshold slope [2]. Confirming the simulation results with experimental results for the temperature in the subthreshold device substantiates the accuracy of the methodology for determining the temperature throughout the device [2]. This methodology, now verified by comparison with experimental results for n-channel MOSFETS, will be applied to the study of CMOS circuits.

A Mathematical Model for the Common-Drain Amplifier Using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

This paper presents a new mathematical model created for the common-drain amplifier using metal-ferroelectric-semiconductor field effect transistors (MFSFET). The model developed in this paper is based upon empirical data collected through experimentation with the common-drain amplifier while using a MFSFET. Several parameters are considered when calculating the output voltage, such as varying gate capacitance, input voltage, quiescent point, and power supply voltages. A comparison between collected and modeled data is presented as verification of the model's performance when applied to the common-drain configuration.

A 1.5–9.6 GHz Monolithic Active Quasi-Circulator in 0.18 $\mu{\rm m}$ CMOS Technology

An active quasi-circulator MMIC was designed and fabricated in a standard 0.18-mum CMOS technology. The quasi-circulator combines common-source, common-gate, and common-drain configurations to improve the isolation between ports, and has an insertion loss less than 6 dB and an isolation better than 18 dB over 1.5-9.6 GHz.

Monolithic image-rejection optoelectronic up-converters that employ the MMIC process

The authors present very small 30-GHz-band monolithic image-rejection optoelectronic up-converters that employ the HEMT MMIC process for the first time. MMIC HEMT optoelectronic mixers are characterized by their direct photodetection and nonlinear characteristics. It is shown that common-source configurations have higher response than common-drain configurations, and up-converter applications are preferable to down-converter applications based on the HEMT direct photodetection characteristics. These characteristics are used to realize 30-GHz-band monolithic image-rejection optoelectronic up-converters. An in-phase divider and a branch-line hybrid with two HEMT optoelectronic mixers are successfully integrated in an MMIC chip with an area of 1.5 mm*1.1 mm. Fundamental performance is demonstrated and excellent wideband performance, which comes from the well-balanced operation of monolithic integrated circuits, is confirmed. These monolithic optoelectronic mixers can be used to realize compact and cost-effective one-chip optical receivers, for fiber optic links which support millimeter waves. >

Common-Drain Flip-Chip GaAs FET Oscillators

GaAs FET oscillators with flip-chip mounted devices in a novel common-drain configuration are described. It is shown how common-drain oscillators can achieve low thermal resistance while at the same time minimizing parasitics. It is also shown that broad-band negative resistances can be generated without external feedback elements. This paper also reports experimental results where output powers of 390 mW with 22-percent efficiency at 8.5 GHz and 230 mW with 26-percent efficiency at 11.7 GHz have been demonstrated.

Noise factor contours for field-effect transistors at moderately high frequencies

This analysis of noise behavior is based on an equivalent circuit for the junction field-effect transistor (FET) that was previously published [10]. Since all noise sources in this equivalent circuit are uncorrelated and all significant parasitic elements are already considered, one may apply an easy and direct calculation for the noise factor, which is carried out for the common source, common gate, and common drain configurations. As a result, the constant noise factor contours are represented as circles in the plane of the complex source admittance Y <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</inf> . This plot of circles is valid above 1/f noise up to moderately high frequencies, and is arrived at by a frequency-dependent normalization of the axis. It is shown that the plot is fully characterized by two frequency-dependent values: the optimum source admittance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Y_{8} {opt}</tex> and the minimum noise factor F <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</inf> , both being derived from the small-signal equivalent circuit of the FET and the bias condition. The results are in agreement with the commonly held opinion that the noise factor does not differ very much for the three basic configurations [9]. Finally, the theoretical results are verified by measurements at 30 and 60 MHz.