Combinational Logic Circuits Research Articles

A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits

Nano-scale devices are continuously shrinking, operating at lower voltages and higher frequencies. This makes them more susceptible to environmental perturbations and distinguished by their high dynamic fault rates. Redundancy techniques are widely used to increase the reliability of combinational logic circuits. In this work, soft error reliability is improved by using such techniques, and based on probability of occurrence for combinations at the outputs of circuits. A generalized modular redundancy scheme to enhance the reliability of combinational circuits is proposed. Additionally, several aspects regarding the application of this scheme are explored. This comprises types of redundant modules, complexity of voters and single versus multiple outputs protection. Also, a methodology for applying the generalized modular redundancy scheme is developed. Reliability analysis for various benchmarks from the LGSynth91 suite shows that the proposed methodology can achieve reliability figures higher than that of triple modular redundancy. In general, significant overhead savings are accomplished in addition to that superior reliability.

Optimization of Combinational Logic Circuits with Genetic Programming

In this paper we research the possibility of automated combinational logic circuit (CLC) design using evolutionary computation. We propose and develop a genetic programming method which is able to construct a CLC based on the given truth tables, where the focus is to minimize the number of logic gates while accuracy is not compromised. We tested the proposed approach and compared the results both with MGA and NGA automatic methods as well as with the results obtained by human designers. Results show that our algorithm is superior to other methods as it can find correct circuits with fewer specified elements. The experiments performed on larger examples show good performance and scalability of the proposed evolutionary approach. DOI: http://dx.doi.org/10.5755/j01.eee.19.7.5169

Experimental Estimation of the Window of Vulnerability for Logic Circuits

Accurate estimation of single event upset rates for complex combinational logic circuits is extremely challenging due to the difficulties involved in calculation of different masking factors. This paper introduces the concept of an effective value of the window of vulnerability which is calculated experimentally for 28 nm bulk CMOS combinational logic circuits. Results suggest that the window of vulnerability for different input conditions of the same circuit are similar but that of different circuits could differ. The difference in gate type and topology is identified as the key reason for the differences in window of vulnerability. The window of vulnerability due to alpha particle irradiation for different circuits is between 30-60 ps which compares reasonably with SET pulse-width distributions reported in the past. The effective value of the window of vulnerability could be used to simplify logic error rate calculations.

Design of synthetic biological logic circuits based on evolutionary algorithm

The construction of an artificial biological logic circuit using systematic strategy is recognised as one of the most important topics for the development of synthetic biology. In this study, a real-structured genetic algorithm (RSGA), which combines general advantages of the traditional real genetic algorithm with those of the structured genetic algorithm, is proposed to deal with the biological logic circuit design problem. A general model with the cis-regulatory input function and appropriate promoter activity functions is proposed to synthesise a wide variety of fundamental logic gates such as NOT, Buffer, AND, OR, NAND, NOR and XOR. The results obtained can be extended to synthesise advanced combinational and sequential logic circuits by topologically distinct connections. The resulting optimal design of these logic gates and circuits are established via the RSGA. The in silico computer-based modelling technology has been verified showing its great advantages in the purpose.

A New Approach for Implementation and Simulation Study Of Digital Circuits using CEDAR Logic

This paper advocates the use of free and open source interactive computerized design tool "Cedar Logic” for the design of combinational and sequential logic circuits. This tool provides a modern approach to fill the gap in the currently available computer based teaching software, with the purpose of providing alternative-mode subject delivery. The Cedar Logic is used to show the link between Boolean algebra and combinatorial and sequential circuits. Each circuit introduces new concepts and produces the complete design of a stand-alone apparatus that is fun and interesting to use.

Synthesis, sensor activity and logic behavior of a highly water-soluble naphthalimide derivative

Herein we report on the design, synthesis and sensor activity of novel highly water-soluble 9,10-dihydro-7H-imidazo[1,2-b]benz[d,e]isoqionolin-7-one. The novel compound was configured as a “fluorophore-spacer-receptor” system. Due to the simultaneously photoinduced electron transfer and internal charge transfer, the designed fluorophore was able to act as a pH-probe via an “off-on-off” fluorescence sensing mechanism. Several logic functions (INH, XNOR, AND, XOR, NAND and OR) using acid and base as chemical inputs could be performed and combinatorial logic circuits (digital comparator and a half-adder) could be designed on the pH induced changes in spectral properties of the novel molecule. The selectivity of the pH sensor toward protons in commonly used buffer solutions and in the presence of transition metal cations (Co2+, Cu2+, Fe3+, Ni2+, Pb2+, Zn2+, Hg2+ and Ag+) was studied by monitoring the changes of its fluorescence intensity. The tested metal ions exerted a minor quenching effect (below 10%) suggesting that the synthesized compound is highly selective to the proton in the pH range between 3 and 10.

Multi-bit binary decoder based on Belousov-Zhabotinsky reaction

It is known that Belousov-Zhabotinsky (BZ) reaction can be applied to chemical computation, e.g., image processing, computational geometry, logical computation, and so on. In the field of logical computation, some basic logic gates and basic combinational logic circuits, such as adder, counter, memory cell, have already been implemented in simulations or in chemical experiments. In this paper, we focus on another important combinational logic circuit, binary decoder. Integrating AND gate and NOT gate, we first design and implement a one-bit binary decoder through numerical simulation. Then we show that one-bit decoder can be extended to design two-bit, three-bit, or even higher bit binary decoders by a cascade method. The simulation results demonstrate the effectiveness of these devices. The chemical realization of decoders can guide the construction of more sophisticated functions based on BZ reaction; meanwhile, the cascade method can facilitate the design of other combinational logic circuits.

Dual-Edge Triggered T Flip-Flop Structure Using Quantum-Dot Cellular Automata

As an emerging nanotechnology, quantum-dot cellular automata (QCA) has the potential to be used for next generation VLSI. Various designs of combinational logic circuits have been proposed for QCA implementation, but sequential circuit design is limited due to the lack of high-performance QCA flip-flops. After an introduction on QCA and dual-edge triggered (DET) flip-flops, a new QCA DET T flip-flop following a pulsed latch scheme is presented. The proposed T flip-flop is simulated using QCADesigner simulator and its logic functionality is verified. The same data throughput of the DET flip-flop can be achieved while operating at half the clock frequency of a single-edge triggered (SET) counterpart. The proposed flip-flop is promising in building QCA sequential circuits with low power and high performance.

Implementation of An Optimized and Pipelined Combinational Logic Rijndael S-Box on FPGA

In this paper, presents an optimized combinational logic based Rijndael S-Box implementation for the SubByte transformation(S-box) in the Advanced Encryption Standard (AES) algorithm on FPGA. S-box dominated the hardware complexity of the AES cryptographic module thus we implement its mathematic equations based on optimized and combinational logic circuits until dynamic power consumption reduced. The complete data path of the S- box algorithm is simulated as a net list of AND, OR, NOT and XOR logic gates, also for increase in speed and maximum operation frequency used 4-stage pipeline in proposed method. The proposed implemented combinational logic based S-box have been successfully synthesized and implemented using Xilinx ISE V7.1 and Virtex IV FPGA to target device Xc4vf100. Power is analized using Xilinx XPower analyzer and achieved power consumption is 29 mW in clock frequency of 100 MHz. The results from the Place and Route report indicate that maximum clock frequency is 209.617 MHz.

Two Analytical Methods for Detection and Elimination of the Static Hazard in Combinational Logic Circuits

In this paper, the authors continue the researches described in [1], that consists in a comparative study of two methods to eliminate the static hazard from logical functions, by using the form of Product of Sums (POS), static hazard “0”. In the first method, it used the consensus theorem to determine the cover term that is equal with the product of the two residual implicants, and in the second method it resolved a Boolean equation system. The authors observed that in the second method the digital hazard can be earlier detected. If the Boolean equation system is incompatible (doesn’t have solutions), the considered logical function doesn’t have the static 1 hazard regarding the coupled variable. Using the logical computations, this method permits to determine the needed transitions to eliminate the digital hazard.

Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits

In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gates have the same propagation delay. The main advantages of this method over other techniques are its accuracy, as it is deterministic and it requires less computational effort compared to exhaustive simulation approaches. The methodology uses the Logic Pictures concept for obtaining the nodes’ toggle rates. The proposed method is applied to well-known circuits and the results are compared to exhaustive simulation and Monte Carlosimulation methods.

A Charge Transfer Amplified Fluorescent Hg2+ Complex for Detection of Picric Acid and Construction of Logic Functions

A chemosensor 3 based on the N,N-dimethylaminocinnamaldehyde has been synthesized which shows fluorescence turn-on response with Hg(2+) ions, and the in situ prepared 3-Hg(2+) complex has been used for detection of picric acid via electrostatic interaction and construction of a combinatorial logic circuit with NOR and INHIBIT logic functions.

SEQUENTIAL LOGIC CIRCUITS RELIABILITY ANALYSIS

Reliability analysis using error probabilities for combinational logic circuits has been investigated widely in the literature. Reliability analysis for sequential logic circuits using these methods would be inaccurate because of existence of loops in their architecture. In this paper a new method based on conversion of sequential circuit to combinational one and applying an iterative reliability analysis is developed. A Monte Carlo method-based reliability analysis is introduced for sequential circuits, which is used for first method validation. Experimental results demonstrate good accuracy of the method.

Parallel genetic algorithm for solving the combinational logic circuit design problem on supercluster.

Parallel genetic algorithm for solving the combinational logic circuit design problem on supercluster.

Synthesis and optimization of multiple-valued combinational and sequential reversible circuits with don't cares

In this paper, a synthesis method for combinational multiple-valued reversible logic (MVRL) circuits is proposed. This algorithm can use the don't care values in the synthesis process to obtain the optimal circuit with respect to quantum cost. The binary Fredkin gate is extended to the MVRL Fredkin gate, and its synthesis using 2×2 gates is proposed. Additionally, we have used the algorithm to design sequential MVRL circuits based on the state transition table. We propose three generalized designs for T, D, and JK flip flops (FF). The generalized r-valued T-FF is designed using 2r−3 controlled Cycle gates (r stands for radix). The r-valued D-FF is designed using the new version of the MVRL Fredkin gate. The ternary JK-FF, which performs nine distinct functions, is designed using only seven controlled Cycle gates. These FFs are the essential circuits to design MVRL state machines, and we synthesize the circuits with the minimal number of constant inputs and garbage outputs.

Device-physics-based analytical model for SET pulse in sub-100 nm bulk CMOS Process

Through revising the process of charge collection for reversed drain-bulk junction, a bias-dependent SPICE model is proposed which includes the bipolar amplification effect that cannot be ignored in PMOS. The model can capture the plateau effect, and produce current and voltage pulse shapes and widths that are consistent with TCAD simulation. Considering the case of connecting load, it is still valid. For combination and sequential logic circuits, the SET pulsewidths and LET upset threshold from SPICE model are consistent with TCAD simulations.

An Efficient Design of 2:1 Multiplexer and Its Application in 1-Bit Full Adder Cell

A multiplexer, sometimes referred to as a mux, is a device that selects between a numbers of input signals. It is a combinational logic circuit. It is a unidirectional device and used in any application in which data must be switched from multiple sources to a destination. This paper represents the simulation of different 2:1 Multiplexer Structures and their comparative analysis on different parameters such as power supply voltage, operating frequency, temperature and area efficiency etc and its application in 1 bit full adder cell. All the simulations have been carried out on BSIM 3V3 90nm technology at Tanner EDA tool. General Terms 2:1 multiplexer, Power-delay product and Speed.

Error Rate Estimation for Defective Circuits via Ones Counting

With VLSI circuit feature size scaling down, it is becoming more difficult and expensive to achieve a desired level of yield. Error-tolerance employs defective chips that occasionally produce erroneous yet acceptable results in targeted applications, and has been proposed as one way to increase effective yield. These chips are characterized by criteria set by specific applications. Error rate, an upper-bound on how frequent errors occur at an output, is one such criterion. In this article we focus on the following problem: given a combinational logic circuit that is defective, and hence occasionally produces an erroneous output, how can we determine the error rate of each output line by using ones counting? The results of this work can also be used for runtime error estimation in aging systems and in environments where soft-errors are produced.

Improvement of Optimization in Design of Synchronous Sequential Circuits by Using Evolvable Hardware

Evolvable hardware is a new method for designing the digital logic circuits. In this paper, a method has been presented for designing the synchronous sequential logic circuit by using the evolvable hardware. In this approach, the sequential logic circuit is divided into two sections; the combinational logic circuit and DFFs. The combinational logic part is designed by using a constant structure and their connections are set with genetic algorithm (GA). The results show that our method can reduce the average number of generations by limitation the search space.

The impact of Miller and coupling effects on single event transient in logical circuits

With feature size scaling down, Miller feedback effects of gate-to-drain capacitance for transistors and coupling effects between interconnects will dramatically affect single event transient (SET) generation and propagation in combinational logic circuits. Two ways of ICs are arranged: linear and “S” types. For pulse width and delay time, SET propagations in two layouts of digital circuits are compared under considering the coupling effects between interconnects. An analytical model is used to describe the impact of Miller and coupling effects on SET propagation. A criterion for SET occurrence in digital circuits with effects of coupling and Miller feedback is presented. The influence of temperature and technology node on SET generation and propagation is analyzed. The results indicate that (1) the existence of these effects will improve the critical charge for SET generation and also reduce the estimated SER, and (2) the way of “S” type is more immune to SET than the scheme of linear.