Abstract
With feature size scaling down, Miller feedback effects of gate-to-drain capacitance for transistors and coupling effects between interconnects will dramatically affect single event transient (SET) generation and propagation in combinational logic circuits. Two ways of ICs are arranged: linear and “S” types. For pulse width and delay time, SET propagations in two layouts of digital circuits are compared under considering the coupling effects between interconnects. An analytical model is used to describe the impact of Miller and coupling effects on SET propagation. A criterion for SET occurrence in digital circuits with effects of coupling and Miller feedback is presented. The influence of temperature and technology node on SET generation and propagation is analyzed. The results indicate that (1) the existence of these effects will improve the critical charge for SET generation and also reduce the estimated SER, and (2) the way of “S” type is more immune to SET than the scheme of linear.
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