Combinational Path Delay Research Articles

Error Detection and Correction for Golay Code & Extended Golay Code using Cyclic Redundancy Check

In this paper certain optimization techniques are proposed to reduce the encoder and decoder computation time of cache memory that is affected by soft error and by implementing ECC such as cyclic and block codes. Error that is adjacent by a width of three and two bits are the prime concern of this thesis. Optimised Golay code (23, 12) and new block code size (32, 19) which is also optimised are presented. Nevertheless, cyclic code is efficient compared with block code however, the prime concern of the thesis is to address the triple and double adjacent errors which also includes single bit error, in this regard built-in capability of Golay code is optimised and used for comparison. The extended Golay code is implemented in term of number of slice, number of LUT and maximum combinational path delay compared with existing Golay code.

Model-Based Hardware-Software Codesign of ECT Digital Processing Unit

Image reconstruction algorithm and its controller constitute the main modules of the electrical capacitance tomography (ECT) system; in order to achieve the trade-off between the attainable performance and the flexibility of the image reconstruction and control design of the ECT system, hardware-software codesign of a digital processing unit (DPU) targeting FPGA system-on-chip (SoC) is presented. Design and implementation of software and hardware components of the ECT-DPU and their integration and verification based on the model-based design (MBD) paradigm are proposed. The inner-product of large vectors constitutes the core of the majority of these ECT image reconstruction algorithms. Full parallel implementation of large vector multiplication on FPGA consumes a huge number of resources and incurs long combinational path delay. The proposed MBD of the ECT-DPU tackles this problem by crafting a parametric segmented parallel inner-product architecture so as to work as the shared hardware core unit for the parallel matrix multiplication in the image reconstruction and control of the ECT system. This allowed the parameterized core unit to be configured at system-level to tackle large matrices with the segment length working as a design degree of freedom. It allows the trade-off between performance and resource usage and determines the level of computation parallelism. Using MBD with the proposed segmented architecture, the system design can be flexibly tailored to the designer specifications to fulfill the required performance while meeting the resources constraint. In the linear-back projection image reconstruction algorithm, the segmentation scheme has exhibited high resource saving of 43% and 71% for a small degradation in a frame rate of 3% and 14%, respectively.

Real Time Implementation of SIGN LMS Adaptive Filters using Xilinx System Generator

Sign Least Mean Square (SLMS) adaptive filter can adapt dynamically based on corresponding filter output. One of the major applications of adaptive filter is Noise cancellation. In real time applications like medical computing, speed of the process developing hardware is essential hence the hardware realization of SLMS adaptive filter using Xilinx System generator is proposed in this work. The propose architecture aims to reduce convergence rate, path delay and increasing speed. In this work (i) Modified architecture is designed for a 8-tap SLMS adaptive filter and (ii) multiplier less structure for Modified DLMS Filter. The designed architecture tested for ECG signal. The functionality of the algorithm is verified in MATLAB with various ECG data from the MIT-BIH database as input. Both LMS and SLMS are designed, simulated, synthesized and implemented in Virtex-5 FPGA using Xilnix ISE 14.3 . The result shows 5% decrease in total real time router completion and also decrease in the number of adders and subtractors, the maximum combinational path delay has been reduced by 48.84% in Systolic Sign LMS Filter when compared to LMS Filter.

Heterogeneous Adder Based FIR Filter Design And Simulation

The finite impulse response (FIR) is one of the important filters in digital signal processing (DSP) as it responds for a finite duration and settles to zero on the finite time. Digital FIR filters are programmable in nature and its behavior can be understood with the help of the program and can be easily programmed for the memory of a processor. The digital filters can be replaced without change of the hardware or the external circuitry. The 7 tap FIR filter needs 16 numbers of multipliers and 9 adders which are used in parallel form. The paper focused on the chip design and implementation of the FIR filter with a decimal adder and heterogeneous adder is done using VHDL programming in Xilinx 14.2 ISE software and the same is synthesized on SPARTAN - 3E FPGA to verify the results. Moreover, the functional simulation is done in Modelsim 10.0 software. Hardware utilization parameters, combinational path delay, memory utilization parameters are directly extracted from the Xilinx software for FIR filter architecture based on decimal adder and heterogeneous adders. The comparative analysis of the FIR filter is done with heterogeneous adder architecture lead an area and delay efficient design for DSP applications

Performance Assessment of Different VLSI Architectures for Data Comparators for Cost Effective Sorting Networks

Noise removal is one of the major requirements in image, speech and signal processing applications. Impulse noise removal in image processing uses median filters. For edge preservation in image processing this acts as one of the best alternative non-linear technique to linear filtering. Real time hardware implementation of median filters has major concern of sorting networks. Efficient VLSI implementation of sorting network in terms of hardware complexity is of greater importance. This work provides a comparison of existing six data comparators and also proposes three modified data comparators in terms of their hardware complexity, area, power and speed. All the comparators were designed using verilog HDL and were targeted for xa6slx4-3-csg225using Xilinx ISE 9.2i FPGA design suite. From the results Modified Twos Complement Based Data Comparator is the minimum area required architecture with maximum combinational path delay and also with minimum number of LUTs used. The drawback of this architecture is the maximum memory requirement. The Modified Multiplexer Based Data Comparator and Modified Decoder Based Data Comparator architectures are suitable for memory efficient design.

An improved wavelet-based signal-denoising architecture with less hardware consumption

In this paper, we propose the VLSI implementation of a wavelet packet transform-based architecture. Moreover, the proposed architecture is compared to the wavelet transform architecture in terms of their signal denoising capabilities, hardware resources used, maximum operating frequency and maximum combination path delay. The Wavelet packet transform architecture is designed and implemented for db2 and db3 wavelet types. For the proposed real-time VLSI implementation, the Xilinx Spartan-6 series FPGA platform is used. Simulation results show that the proposed architecture implementation results in an improved performance for ECG signals taken from the Fantasia Database as well as from the self-recorded database, as compared to the WT wavelet architectures which result in distorted outputs. Moreover, from the synthesis results, it is concluded that the proposed architecture implementation requires significantly less hardware as compared to the WT architectures considered. In terms of LUTs, the proposed architecture consumes 38.20 percent and 84.96 percent less resources than the WT-db2 and WT-db5 architectures, respectively. Similarly, in terms of slice registers, the proposed architecture consumes, respectively, 21.39 percent and 75.61 percent less resources than the WT-db2 and WT-db5 architectures. Furthermore, the maximum operating frequency of the proposed architecture is 180.278 MHz as compared to that of 195.496 MHz and 121.038 MHz for the WT-db2 and WT-db5 architectures respectively. The maximum combinational path delay of the proposed architecture is 48.109 ns, as compared to that of 13.784 ns and 15.202 ns for the WT-db2 and WT-db5 architectures, respectively.

Timing violation reduction in the FPGA prototyped design using failed path fixes and time borrowing techniques

<span>A fascinating property of a latch-based design is that the combinational path delay is allowed to be longer than the clock cycle as it can borrow time from the shorter paths in the subsequent logic states. Time borrowing technique is a common method used to satisfy timing violation in an FPGA prototyped design. The purpose of this paper is to review the current methodology involved in SoC design prototyping using a Synopsys Protocompiler and HAPS-80 platform and propose an approach by fixing the failed path in a latch due to the gated clock conversion (GCC) process during the synthesis stage which could lead to the timing violation. Two techniques are applied in this paper namely time borrowing technique and our proposed technique, Failed Path Fixes to reduce the timing violation in the FPGA prototyped design. The result shows that the applied techniques are able to close the timing violation in the design with an average of 90% improvement.</span>

VLSI implementations of retimed high speed adaptive filter structures for speech enhancement

This paper presents FPGA implementation of retimed high speed adaptive filter structures for speech enhancement. In this work, various high speed adaptive filtering structures for noise cancellation are implemented for Xilinx Spartan-6 series and Virtex-4 series FPGA platforms. It has been observed that various VLSI implementations vary considerably in clock speed, hardware requirements, latency and cost. For instance, for the Spartan-6 series FPGA platform implementation, the clock speed of retimed DF-RDLMS implementation is found to be 98.309 MHz whereas that of conventional unretimed DF-LMS structure is 85.485 MHz, thereby having an improvement of 15% in clock speed. Similarly, for the Virtex-4 series FPGA platform implementation, the clock speed of retimed DF-RDLMS implementation is found to be 88.176 MHz whereas that of conventional unretimed DF-LMS structure is 75.855 MHz, thereby having an improvement of 16.5% in clock speed. The VLSI implementation and the performance analysis provides crucial information about an algorithm structure such as hardware requirements, power consumption and real-time performance. Performance of the implemented structures have been checked in terms of operating frequency, maximum combinational path delay, latency, and power consumption.

Review Paper on Radix-2 DIT and DIF Fast Fourier Transform

With the arrival of recent generation in the field communication, there is also an ever growing demand for low power consumption and minimum consumed It is also a well-known reality that the chip location and maximum combinational path delay (MCPD) unit forms an indispensable a part of processor layout. Due to this regard, high speed and low area architectures grow to be the want of the day. A fast Fourier transform (FFT) is any rapid algorithm for computing the DFT. The decimation (DIT) fast Fourier remodel (FFT) very often has advantage over the decimation-in-frequency (DIF) FFT for most real valued programs, like speech/photo/video processing, biomedical sign processing, and time-collection evaluation, and so on., since it does now not require any output reordering.

Area Efficient High Speed Approximate Multiplier with Carry Predictor

Multimedia and image processing applications, may tolerate errors in calculations but still generate meaningful and beneficial results. This work deals with a high speed approximate multiplier with TDM tree and carry prediction circuit. The modified multiplier utilizes an optimised TDM carry save tree which reduces the device utilization on FPGA as well as the combinational path delay and power consumption. The proposed design is analyzed using the simulation and implementation results on Xilinx Spartan 3E family.

Performance Analysis of Robust Recursive Least Square and its Lattice Structure for Noise Cancellation in ECG Signals

Bio signals are non-stationary signals corrupted by various environmental noises like Power Line Interference (PLI), Baseline Drift, Instrumentation noise generated by electronic devices, Motion artifacts, Electrosurgical Noise, Electrode Motion (EM) noise. Thus removal of the environmental noises becomes a challenging task. The filters with fixed coefficients cannot be applied because the human behavior is not exactly known at any point of time. An adaptive filter has flexible ability to modify the system parameters and adjusts the input signal to bring out optimal performance. This paper introduces the application of Robust Recursive Least Algorithm (RRLS) for adaptive noise cancellation. The Robust RLS algorithm is used to find the optimal value of the regularization parameter (delta) and forgetting factor (lambda). By maintaining a variable forgetting factor the convergence of the algorithm is faster. Architectural modifications such as direct form and transpose form structures are also carried out in filter structure to analyze the delay. To reduce the computational complexity of the RRLS algorithms Lattice RLS Structures are also studied for its performance. Accordingly 4 tap, 8 tap and 16 tap RRLS filters in both direct form and transpose forms are designed and implemented in Virtex5 FPGA kit. Also 4 tap, 8 tap and 16 tap lattice filters and its pipelined version are designed and implemented. The designed filters are tested using various ECG signals taken from MIT BIH database. Result shows an improvement of 10.88% of SNR for PLI Noise and 12.3% of SNR for EM Noise compared to RRLS Filter. From the overall analysis, the number of LUT‘S required for Lattice RLS has been reduced by 12.1% for 8-Tap compared to Robust RLS filter. It is also observed that the combinational path delay of pipelined lattice RLS is reduced by 80.7% for 8-Tap compared to Robust RLS filter.

IMPLEMENTATION OF ARITHEMATIC OPERATIONS USING VEDIC MATHEMATICS

Abstract Vedic maths is the ancient Indian mathematics, it has 16 sutras for the calculations. These sutras can be used to solve very complex equation and operations. This paper seeks to present an integrated approach to implement the ALU using Vedic methods wherein the sutras are chosen and implemented for performing the basic operations like addition, subtraction, multiplication and logical operations. Sutras from vedic mathematics are selected according to the operations being performed and the verilog code is written and simulated for their implementation. The logical proof and explanation for the sutra’s application is given in detail. These sutras are completely based on logical and rational reasoning. The sutras used in this paper for implementation of above mentioned operations are all for general case. The timing report is generated showing minimum period, input arrival time before clock, maximum output required time after clock and maximum combinational path delay.

Logic Optimization Using Technology Independent MUX Based Adders in FPGA

Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. Therefore, careful optimization of the adder is of the greatest importance. This optimization can be attained in two levels; it can be circuit or logic optimization. In circuit optimization the size of transistors are manipulated, where as in logic optimization the Boolean equations are rearranged (or manipulated) to optimize speed, area and power consumption. This paper focuses the optimization of adder through technology independent mapping. The work presents 20 different logical construction of 1-bit adder cell in CMOS logic and its performance is analyzed in terms of transistor count, delay and power dissipation. These performance issues are analyzed through Tanner EDA with TSMC MOSIS 250nm technology. From this analysis the optimized equation is chosen to construct a full adder circuit in terms of multiplexer. This logic optimized multiplexer based adders are incorporated in selected existing adders like ripple carry adder, carry look-ahead adder, carry skip adder, carry select adder, carry increment adder and carry save adder and its performance is analyzed in terms of area (slices used) and maximum combinational path delay as a function of size. The target FPGA device chosen for the implementation of these adders was Xilinx ISE 12.1 Spartan3E XC3S500-5FG320. Each adder type was implemented with bit sizes of: 8, 16, 32, 64 bits. This variety of sizes will provide with more insight about the performance of each adder in terms of area and delay as a function of size.

Design of 4x4 bit Vedic Multiplier using EDA Tool

The need of high speed multiplier is increasing as the need of high speed processors are increasing. A Multiplier is one of the key hardware blocks in most fast processing system which is not only a high delay block but also a major source of power dissipation. A conventional processor requires substantially more hardware resources and processing time in the multiplication operation, rather than addition and subtraction. This paper presents a high speed 4x4 bit Vedic Multiplier (VM) based on Vertically & Crosswise method of Vedic mathematics, a general multiplication formulae equally applicable to all cases of multiplication. It is based on generating all partial products and their sum in one step. The coding is done in VHDL (Very High Speed Integrated Circuit Hardware Descriptive Language) while the synthesis and simulation is done using EDA (Electronic Design Automation) tool XilinxISE12.1i. The combinational path delay of 4x4 bit Vedic multiplier obtained after synthesis is compared with normal multipliers and found that the proposed Vedic multiplier circuit seems to have better performance in

Effect of glitches against masked AES S-box implementation and countermeasure

Masking of gates is one of the most popular techniques to prevent differential power analysis (DPA) of AES algorithm. It has been shown that the logic circuits used in the implementation of cryptographic algorithms leak side-channel information inspite of masking, which can be exploited, in differential power attacks. The phenomenon in CMOS circuits responsible for the leakage of masked circuits is known as glitching. Motivated by this fact, the authors analyse the effect of glitches in CMOS circuits against masked implementation of the AES S-box. The authors explicitly demonstrate that glitches do not affect always. There exists a relation between combinational path delay of the circuit and timing difference of input vectors to the circuit, which has a bearance on the amount of information leaked by the masked gates. A balanced masked S-box circuit is proposed where the inputs are synchronised by sequential components. Detailed SPICE results are shown to support the claim that the modifications indeed reduce the vulnerability of the masked AES S-box against DPA attacks.

Combining ESOP minimization with BDD-based decomposition for improved FPGA synthesis

This paper proposes a novel method to improve the utilization efficiency and performance of field-programmable gate arrays (FPGAs). The proposed method, ExorBDD, uses a stage of exclusive-sum-of-product (ESOP) minimization, followed by a stage of decomposition using binary decision diagrams (BDDs). For exclusive OR (XOR)-intensive circuits, experiments were conducted on 19 MCNC benchmark parity circuits (ranging from 5 to 25 inputs), as they are the most representative case of XOR-intensive circuits. The results using the proposed approach show significant improvements over Exorcism4, BDS, and commercial tools. On average, the new approach uses only 30.3% as many look-up tables as are used by Xilinx tools (and only 16.4% in comparison to Altera). On average, the new approach has a maximum combinational path delay of 89.2% compared to the delay with Xilinx tools (80.3% compared to Altera). Experiments were also conducted on non-XOR-intensive circuits. These results show that ExorBDD also performs well for arbitrary circuits.

Efficient Realization of Parity Prediction Functions in FPGAs

In this paper, we propose an AND/XOR-based technology mapping method for efficient realization of parity prediction functions in field programmable gate arrays (FPGAs). Due to the fixed size of the programmable blocks in an FPGA, decomposing a circuit into sub-circuits with appropriate number of inputs can achieve an excellent implementation efficiency. Specifically, the proposed technology mapping method is based on Davio expansion theorem. The AND/XOR nature of the proposed method allows it to operate on XOR intensive circuits, such as parity prediction functions, efficiently. We conduct experiments using the parity prediction functions with respect to MCNC benchmark circuits. With the proposed approach, the number of configurable logic blocks (CLBs) is reduced by 67.6% (compared to speed-optimized results) and 57.7% (compared to area-optimized results), respectively. The total equivalent gate counts are reduced by 65.5%, maximum combinational path delay is reduced by 56.7%, and maximum net delay is reduced by 80.5% compared to conventional methods.

Optimal time borrowing analysis and timing budgeting optimization for latch-based designs

An interesting property of a latch-based design is that the combinational path delay is allowed to be longer than the clock cycle as long as it can "borrow" time from the shorter paths in the subsequent logic stages. This gives designers a lot of flexibility in designing circuits, especially high performance ones. However, it also increases the complexity in timing analysis. Finding the best clock period or determining how much time to borrow from the subsequent logic stages is difficult especially for designs containing multiple clocks, mixed-clock paths, user-specified multicycle paths, and false paths. In this article, we formulate the time borrowing problem as a linear programming problem. An optimal time borrowing solution can be found by solving the formulation. Based on this time borrowing solver, algorithms are proposed for timing optimization to achieve the optimal clock period. Experimental results show our algorithm is efficient and yields very good results.