Abstract
Image reconstruction algorithm and its controller constitute the main modules of the electrical capacitance tomography (ECT) system; in order to achieve the trade-off between the attainable performance and the flexibility of the image reconstruction and control design of the ECT system, hardware-software codesign of a digital processing unit (DPU) targeting FPGA system-on-chip (SoC) is presented. Design and implementation of software and hardware components of the ECT-DPU and their integration and verification based on the model-based design (MBD) paradigm are proposed. The inner-product of large vectors constitutes the core of the majority of these ECT image reconstruction algorithms. Full parallel implementation of large vector multiplication on FPGA consumes a huge number of resources and incurs long combinational path delay. The proposed MBD of the ECT-DPU tackles this problem by crafting a parametric segmented parallel inner-product architecture so as to work as the shared hardware core unit for the parallel matrix multiplication in the image reconstruction and control of the ECT system. This allowed the parameterized core unit to be configured at system-level to tackle large matrices with the segment length working as a design degree of freedom. It allows the trade-off between performance and resource usage and determines the level of computation parallelism. Using MBD with the proposed segmented architecture, the system design can be flexibly tailored to the designer specifications to fulfill the required performance while meeting the resources constraint. In the linear-back projection image reconstruction algorithm, the segmentation scheme has exhibited high resource saving of 43% and 71% for a small degradation in a frame rate of 3% and 14%, respectively.
Highlights
Electrical capacitance tomography (ECT) is an industrial process tomography technique for imaging materials distributions inside a certain interest area [1, 2]
The ECT system consists of three main components, capacitance sensors, data acquisition unit, and ECT digital processing unit (ECT-DPU) as shown in Figure 1 [4]
This paper proposes a model-based hardware-software codesign flow of the digital processing unit for realization of the image reconstruction and control module of the ECT system on the FPGA SoC platform
Summary
Electrical capacitance tomography (ECT) is an industrial process tomography technique for imaging materials distributions inside a certain interest area [1, 2]. Measured capacitance data are sent wirelessly to a base station attached to ECTDPU where an image reconstruction algorithm is implemented to produce an image describing the material distribution inside the imaging area [5, 6]. An ECT image reconstruction algorithm is realized as a software on a general-purpose processor [7], but in stringent time constraints, a dedicated hardware can be used [6] to achieve the real-time operation. While high flexibility and low design effort can be gained by applying the software implementation, its performance gain is low.
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