The subject of research in the article is qubit-vector models for combinational circuits’ description and procedures for faults deductive simulation based on these models. The object of research is the processes of diagnostic support creation for digital systems based on the usage of vector qubit data. The purpose of the work is to increase the speed and quality of diagnostic support creation for digital devices by creating optimal data structures and deductive fault simulation procedures based on structural-functional models of combinational circuits. The following tasks are solved in the article: analysis of concurrent and sequential conditional operators of hardware description languages and schematic structures into which they are synthesized; development of the procedure for the truth tables (Q-vectors) formation for schematic structures presented by HDL; development of an universal data structure for cubic and analytical deductive faults simulation; vector models improvement of qubit representation of structures and components of digital systems based on address coding of input signals to increase the manufacturability and speed of faults simulation; development of the procedure for obtaining Boolean derivatives by permuting the lines of the truth tables (Q-vectors) and using the XOR operation; development of a data structure for deductive fault simulation based on the cubic representation of digital circuit components. The following methods are used: deductive, cubic, deductive-parallel simulation of faults, faults simulation by deductive Q-vectors. The following results were obtained: the equivalence of concurrent and sequential conditional operators, as well as their schematic implementation in the form of multiplexers, was shown; method of obtaining truth tables of the synthesized circuit structure using TestBench (Xilinx ISE) was proposed; different technologies and data structures of deductive fault simulation for tabular, analytical and qubit methods of digital circuits description were considered; the software implementation of faults cubic deductive simulation is considered and the equivalence of the obtained results for the multiplexers circuits (MUX 2-in-1 and MUX 4-in-1) using the DCP software product was demonstrated. Conclusions: a new Q-method of interpretative faults simulation of digital circuit is proposed, which is characterized by the usage of compact Q-vectors instead of truth tables, which makes it possible to significantly increase the analysis speed due to the addressable formation of the functional primitives outputs and reduce the volume of data structures, which practically makes the method competitive with compilative simulation technologies.