Adaptive DLMS equalizer based on modern FPGA

Abstract

A simple and effective way to implement adaptive equalization schemes in digital communication systems is to implement them on general-purpose microcontrollers. However, increasing the order of the equalizer, which leads to increase the time to obtain the output sample, at the same time leads to decreasing maximum allowable symbol rate. It makes the implementation based on microcontrollers impractical for use in modern high-speed communication protocols. A more suitable computing platform for implementing LMS algorithms is FPGA, where there is no dependence of output sample obtaining time on equalizer order. In order to derive the error signal at the equalizer output from the last (actual) output sample, the estimation of the error signal in the FPGA is required to occur during the same clock period as the calculation of the output signal sample. Trying to fit all the necessary operations into one clock period leads to decrease maximum allowable clock frequency and inefficient using of computing resources within the FPGA. The solving of this problem is to use the Delayed LMS (DLMS) algorithm, invented in the late 80s. The essence of DLMS algorithm is to pipeline both the blocks for calculating the equalizer coefficients and the output samples. The meaning of pipelining is to install synchronous delay elements (D-flip-flops) between the elements of combinatorial logic, which makes it possible to increase the clock and symbol frequency of the equalized signal. The disadvantage of this method is the presence of the synchronous delay of several clock cycles and, as consequence, using of irrelevant error signal for updating coefficients. Retiming procedure is used to optimally distribute synchronous delays to maximize system clock frequency. This article describes the DLMS equalizer and shows the effectiveness of DLMS algorithms implementation on FPGA. The effectiveness of algorithms, which have been used for the retiming procedure is shown. Diagrams of BER(SNR) and BER (Doppler frequency shift) of LMS and DLMS equalization circuits are presented. Obtained results facilitate transfer of demodulator circuit of existing modem from the Zynq microcontroller part built into the Xilinx XC7Z020 FPGA to its programmable logic part in order to increase the performance of the modem receiver to solve current and future challenges.