A Novel Clock Duty-Cycle Corrector of DSP Systems

Abstract

A novel 50% duty-cycle corrector (DCC) of digital signal processing (DSP) systems, designed with a purely digital phase-blending technique, is presented in this paper. The novel features of the proposed DCC includes a higher reliability against process, voltage and temperature variation due to the use of the synchronous mirror delay (SMD) technique, no-skew output clock, and a much faster duty-cycle correction speed compared to conventional DCC's. When designed with a 0.13-μm CMOS technology, the acceptable duty-cycle of the input signal ranges from 10% to 90% when the clock frequency is 400 MHz and the correction operation spends 4 clock cycles with the corrected duty-cycle varying from 48% to 52%.