Combinational Research Articles

The combinatorics of Farey words and their traces

We introduce a family of 3 -variable ‘Farey polynomials’ that are closely connected with the geometry and topology of 3 -manifolds and orbifolds as they can be used to produce concrete realisations of the boundaries and local coordinates for one-dimensional (over \mathbb{C} ) deformation spaces of Kleinian groups. As such, this family of polynomials has a number of quite remarkable properties. We study these polynomials from an abstract combinatorial viewpoint, including a recursive definition extending that which is known in the literature for the special case of manifolds, even beyond what the geometry predicts. We also present some intriguing examples and conjectures which we would like to bring to the attention of researchers interested in algebraic combinatorics and hypergeometric functions. The results in this paper additionally provide a practical approach to various classification problems for rank 2 subgroups of \operatorname{PSL}(2,\mathbb{C}) since they, together with other recent work of the authors, make it possible to provide certificates that certain groups are discrete and free, and effective ways to identify relators.

Analyzing Multilayer Graphene Nanoribbon‐Based Via‐Interconnect Scheme: Prospects and Challenges for Monolithic 3D Integrated Circuits

This article presents a multilayer graphene nanoribbon (MLGNR)‐based single‐tier on‐chip nanoscale via‐interconnect scheme (VIS), which combines the vertical MLGNR via and horizontal MLGNR interconnect, as a prospect for monolithic 3D (M‐3D) integrated circuits (ICs). To go beyond the simplifying assumptions of perfect MLGNR and conventional skin‐effect, this study incorporates the impact of edge‐ and substrate‐induced scatterers in a realistic MLGNR and considers the 1D skin depth formula for MLGNR‐based on‐chip interconnect and via. A combined equivalent circuit model is developed to analyze the challenges induced by scatterers, skin‐effect, and crosstalk effect in perfect MLGNR VIS (P‐VIS) and realistic MLGNR VIS (R‐VIS). The results show that for width in the range of 5–30 nm, P‐VIS outperforms R‐VIS in terms of crosstalk delay. Moreover, at high frequencies ranging from 1 to 104 GHz with a width of 16 nm, R‐VIS demonstrates a performance decline of 243.18% (5.3934 × 103%) for L = 4.8 μm (1 mm), respectively, in comparison with P‐VIS. Hence, in order to leverage the potential of MLGNR‐based VIS for M‐3D ICs at high frequencies, it is imperative to integrate Li‐intercalation doping and mitigate the impact of edge and substrate scatterers in MLGNR.

Measurement of SET pulse width modulation in CMOS combinational logic by laser-induced fault injection

Measurement of SET pulse width modulation in CMOS combinational logic by laser-induced fault injection

UV LED Printing Device for PCB Fabrication

Photolithography is commonly used to fabricate printed circuit boards (PCBs) in micromanufacturing. It involves UV exposure to pattern portions of a thin film of a substrate before a geometric design is transferred from a photo mask to a light-sensitive substance (photoresist) on the substrate using light. Conventionally, metal halide lamps and UV fluorescent bulbs make up most of the exposure systems during photolithography. However, both systems are highly costly in educational establishments and consume high electrical energy. Moreover, they also have too broad UV radiation and are not appropriate for the sizes of PCBs that need to be mounted on the apparatus. Hence, this innovation aims to create a low-cost, portable UV exposure system that works well in educational settings by utilizing LED illumination technology. In order to manage time, relay, and LCD, these UV LED exposures were built using a combined LED circuit with a controller board. With a dimension of 120 mm by 190 mm and 3 mm LEDs, the UV LED circuit generates a wavelength of 400 to 405 mm for the UV exposure system. Due to its powerful and flexible design capabilities, LED lighting may be integrated in any shape to create highly efficient illumination. The testing result shows that LED lights have higher application efficiency due to its ability to concentrate light in one area. Therefore, well-designed LED illumination systems may deliver light to the intended spot more effectively. They also brighten up instantly when powered on and can be turned on and off repeatedly. This research has highlighted the advantages of LEDs for infrastructure projects, such as exposure systems, which could be further developed for future technology.

Groupoidal realizability for intensional type theory

Abstract We develop realizability models of intensional type theory, based on groupoids, wherein realizers themselves carry non-trivial (non-discrete) homotopical structure. In the spirit of realizability, this is intended to formalize a homotopical BHK interpretation, whereby evidence for an identification is a path. Specifically, we study partitioned groupoidal assemblies. Categories of such are parameterized by “realizer categories” (instead of the usual partial combinatory algebras) that come equipped with an interval qua internal cogroupoid. The interval furnishes a notion of homotopy as well as a fundamental groupoid construction. Objects in a base groupoid are realized by points in the fundamental groupoid of some object from the realizer category; isomorphisms in the base groupoid are realized by paths in said fundamental groupoid. The main result is that, under mild conditions on the realizer category, the ensuing category of partitioned groupoidal assemblies models intensional (1-truncated) type theory without function extensionality. Moreover, when the underlying realizer category is “untyped,” there exists an impredicative universe of 1-types (the modest fibrations). This is a groupoidal analog of the traditional situation.

EnR: extend and reduce methodology to enable formal verification of truncated adders

Abstract Truncated adders are widely used in applications where using lower bit-width is enough to generate the desired outputs. Truncated adders give benefits in area, power, and delay as compared to their non-truncated counterparts. While prior works deal with the formal verification of n-bit adders, there is no prior work dealing with the formal verification of unverified m-bit truncated adders using verified n-bit adder designs, where m < ${< } $ n. In this work, we propose a methodology that enables the verification for any truncated adder designs, irrespective of the architecture, called Extend and Reduce (EnR). EnR uses a three-step methodology to formally verify the truncated adders, which are considered as Design Under Verification (DUV). Firstly, it extends the bit-width of the DUV (truncated adder) to match with the nearest higher 2 n -bit adder, called an Extended Truncated Adder (ETA). Secondly, it reduces off-the-shelf formally verified golden reference adder design by forcing 0’s at the input bits to match it to the extended DUV design and re-synthesizing it to generate a Reduced Golden Adder (RGA). Lastly, a combinational equivalence check is then performed between the ETA and the RGA for formal verification. If the truncated adder is correct, the ETA and RGA are equivalent and vice versa. We evaluate a number and variety of adder designs to show the efficacy of the EnR methodology. We performed the formal verification using Binary Decision Diagrams (BDDs) and And-Inverter Graphs (AIGs). Lastly, we show the scalability of EnR methodology using adders up to a bit-width of 512 bits. ACM CCS Hardware → Arithmetic and datapath circuits; Combinational circuits; Equivalence checking; Functional verification; Electronic design automation.

Effective correction of manifestations of vaginal microflora disorders

Pathological vaginal discharge is one of the main reasons for visiting gynecologists. Despite the abundance of drugs, not all are compliant and quickly effective for pronounced itching and swelling in the introitus area. One of the most common causes of pathological leukemia is vaginal infections, which are represented by three main clinical forms: bacterial vaginosis (BV) – up to 50% of all cases; vulvovaginal candidiasis (CVV) – 20–25% and trichomonas vaginitis (TV) – 15–20% of cases, respectively. In this regard, retrospective analysis shows that patients with BV, KV, TV most often actively turn to a gynecologist or venereologist However, the fact that the cause of pathological whites in more than 30% of cases can be a mixed infection creates problems in treatment with the use of monodrugs (many relapses up to 40% or more). Therefore, for their treatment, it is considered rational to use the concept of the etiotropic approach, based on the local effect of combined vaginal drugs. The role of a combined topical drug, including those with a rapid anesthetic effect, was evaluated. Neo-Penotran Forte L is a logical combination of antibacterial agents and a local anesthetic used to treat manifest forms of vaginal infections and provide rapid relief of intolerable symptoms.

Hamming distances of unsaturated orthogonal arrays

Orthogonal arrays (OAs) are applied in the statistical design of experiments, coding theory, cryptography, various types of software testing and quality control and have many connections to other combinatorial designs. The Hamming distances of OAs play a critical role in many areas such as algebraic combinatorics, quantum information theory, and wireless sensor networks. However, the calculation method of Hamming distances is difficult, especially for mixed orthogonal arrays (MOAs), since they rely on constructions or structures of OAs in many cases. In this article, by using the number of coincidences, we find some OAs with high strength and MOAs with strength 2 and 3, whose Hamming distances do not depend on their structures. We also calculate Hamming distances of a series of unsaturated asymmetrical OAs via their construction methods such as deleting columns, the expansive replacement method, and difference schemes.

Design and Implementation of a 7-Person Voting Device based on Quartus

As the complexity of digital system design continues to increase, efficient and precise decision support systems have become increasingly important. This paper presents the design and implementation of a 7-voter decision system based on Altera’s Quartus software. The voter is applied in the core decision-making process to ensure the accuracy and efficiency of decisions. The study begins by outlining the design principles of the 7-voter decision system, using a design philosophy that minimizes timing delays and optimizes hardware resource utilization. A complex majority voting logic circuit is implemented using high-level hardware description languages (VHDL/Verilog), ensuring the advanced nature and applicability of the voting circuit. In terms of the logical implementation of the voting circuit, the paper conducts an in-depth analysis of the optimization of combinational and sequential logic and standardizes the input and output to enhance the signal stability and the system’s resistance to interference. On the Quartus platform, the design process of the voting system is elaborated in detail, with careful consideration given to boundary conditions and hardware compatibility. The implementation of the voter has undergone rigorous simulation and testing. Strict parameter setting for simulations and waveform analysis confirm the correctness of the circuit, and fault simulation tests further confirm its reliability. Performance indicators such as response time and percentage of resource utilization have been quantitatively analyzed and meet the design objectives set beforehand. Overall, this research not only realizes a highperformance 7-voter decision system but also provides an effective case study for applications on the high-performance Quartus design platform. Future research can build on the current work to further optimize algorithms and hardware, explore the potential for the application of the voter in a broader range of fields, and adapt to the new features of the Quartus platform to achieve more powerful decision support functions.

RISC-V Leads the Future: Evolution and Outlook of CPU Architecture

This essay mainly talked the development of CPU and some instruction set architecture based on RISCV. CPU is known as the Central Processing Unit, the main appliment is RISCV, Also the ARM architecture is characterized by a focus on the balance between low power consumption and high performance. Then X86, its significant advantage is its complex instruction set and excellent performance, so it can handle complex computational tasks. We also explore the Pipeline technology, it is a widely used parallel processing technology today. The design principle is to divide complex, multilevel combinational logic circuits into multiple levels. Then, we find some experiment data to explore our conclusion. We find that each has its own advantages and is better suited to different scenarios. In terms of performance, x86 offers superior capabilities but consumes more power, making it ideal for high-performance computing and server applications. ARM, on the other hand, excels in power efficiency and finds its primary use in mobile devices and embedded systems. RISC-V, known for its flexibility, allows for a balance between performance and power consumption based on specific requirements, making it suitable for highly customizable applications, IoT devices, and emerging high-performance computing markets. The advantages of each architecture in different fields depend on the specific application environment and demands placed on them.

Implementation of a novel secured authentication protocol for cyber security applications

Robust verification protocols are crucial for maintaining the security and reliability of sensitive information due to the increasing complexity of cyber-attacks. This paper introduces a novel 5G Secure Handover Protocol aimed at addressing security and effectiveness issues encountered in existing systems. The proposed protocol is robust against various attacks, including de-synchronization, replay, man-in-the-middle (MITM), denial of services (DoS), and jamming, ensures perfect forward key secrecy, safeguarding communication confidentiality. The proposed protocol utilizes a combination of spiking neural network and fuzzy logic (SNN-FL) techniques that must choose the goal cell as carefully as possible before initiating the transfer process. By combining fuzzy logic and spiking neural networks to reduce handover latency and thwart several types of cyberattacks, the proposed 5G Secure Handover Protocol improves security. Extensive simulations show its efficacy and emphasize its potential for safe communication in large-scale cybersecurity applications. The paper presents a novel secure authentication protocol that significantly reduces handover delays and improves efficiency. Simulations show its resilience against common security threats, protecting sensitive information and maintaining secure communication channels. The protocol, with low communication expenses, complex spatial, and latency for changeover verification, is ideal for large-scale cybersecurity applications, contributing to the development of secure digital authentication mechanisms.

Drain self-blocking ambipolar transistors for complementary circuit applications

The development of complementary metal-oxide-semiconductor field-effect transistor (CMOSFET) based on two-dimensional (2D) materials offers an important opportunity to reduce static power and increase the integration density of integrated circuits. One promising approach to realize these CMOSFETs is to employ ambipolar 2D materials as channel materials with designed device structure to control the carrier transport properties for CMOSFET characteristics. However, these devices always suffer from complex multi-gate electrode structure, and hence face challenges in complicated inter-connection design and excessive voltage source requirement for circuit implementation. Here, we develop a three-terminal CMOSFET using ambipolar 2D material based on the drain electric field-induced carrier injection self-blocking mechanism. The designed drain electrode can effectively suppress carrier injection from the drain to the channel material, while the gate voltage can only regulate carrier injection in the source region. As a result, we can configure the device as either N-field-effect transistors (FET) or P-FET with a high current on/off ratio of over 105 by adjusting the three voltages (gate, source, and drain). Furthermore, we utilize these devices to demonstrate multifunctional wave modulator, low-static-power logic inverter (<5 pW), and combinational logic computing in the form of a compact complementary circuit. Our work would explore an efficient approach for implementing complementary circuits using 2D materials.

A framework to assess the effectiveness index (EI) of the Indian SMEs to integrate lean and sustainability through combined fuzzy logic and systems approach

PurposeTo become a sustainable lean manufacturing (LM) system, an organization must be first distinctly cognizant of the terms “lean” and “sustainability” as they relate to the state of affairs of their particular industry and business. Next, the organization must identify and acquire the necessary qualities it needs to become sustainable in lean philosophy and its practices in the organization. The LM paradigm has been a top priority for many businesses; thus, this article is based on actual research done in Indian small and medium scale organizations to see how widely it is understood and implemented.Design/methodology/approachA framework was developed based on literature review and academic research. A preliminary analysis of a small number of small and medium-sized enterprises (SMEs) that, conceptually, summarizes and demonstrates the concerted efforts that a company may undertake to increase its leanness. This conceptual model was employed to create a questionnaire that was administered to survey the SMEs of India. The information gathered through this questionnaire was analyzed using the model developed by the researchers. Then fuzzy logic and systems approach were used to find out the effectiveness index (EI) of the organization.FindingsThe EI for system leanness at different organizational levels within an organization is determined using fuzzy logic and systems approach for 48 SMEs in different clusters. The average EI of the system was found to be 0.336 on a scale of 0–1 which indicates that the current state of lean implementation and its sustainability is very low and poor in Indian SMEs. This article outlines the key model components and describes how they were applied to analyze the data gathered from an industry study.Research limitations/implicationsThe research aims to make lean continuously sustainable by surfacing and eliminating the wastes in the Indian SMEs whenever it appears rather than using it as a cleaning tool. The present study was focused on India’s southern industrial areas and it was difficult to gather the information around the country due to its diverse industrial culture and geography. Hence, more research and the comparative study of the same that takes into account the various regions of the nation’s industrial lean behavior can be conducted.Practical implicationsThe generalized sustainable lean framework analyzed using fuzzy logic and systems approach gives the current effectiveness of the leanness in SMEs of south India. This model can be effectively implemented in other areas of the nation to identify the scenario of lean and its sustainability and a final comprehensive model can be developed.Originality/valueThere is a dearth of comprehensive studies on the assessment of sustainability of the lean philosophy in Indian SMEs. With the help of combined fuzzy logic and systems approach, the model developed in this study evaluates the sustainability of the lean methodology using the EI used in SMEs by taking into account both the lean and sustainability factors as well as enablers like customer satisfaction, ethics, innovation and technology.

From Quasi-Symmetric to Schur Expansions with Applications to Symmetric Chain Decompositions and Plethysm

It is an important problem in algebraic combinatorics to deduce the Schur function expansion of a symmetric function whose expansion in terms of the fundamental quasisymmetric function is known. For example, formulas are known for the fundamental expansion of a Macdonald symmetric function and for the plethysm of two Schur functions, while the Schur expansions of these expressions are still elusive. Based on work of Egge, Loehr and Warrington, Garsia and Remmel provided a method to obtain the Schur expansion from the fundamental expansion by replacing each quasisymmetric function by a Schur function (not necessarily indexed by a partition) and using straightening rules to obtain the Schur expansion. Here we provide a new method that only involves the coefficients of the quasisymmetric functions indexed by partitions and the quasi-Kostka matrix. As an application, we identify the lexicographically largest term in the Schur expansion of the plethysm of two Schur functions. We provide the Schur expansion of $s_w[s_h](x,y)$ for $w=2,3,4$ using novel symmetric chain decompositions of Young's lattice for partitions in a $w\times h$ box. For $w=4$, this is the first known combinatorial expression for the coefficient of $s_{\lambda}$ in $s_{w}[s_{h}]$ for two-row partitions $\lambda$, and for $w=3$ the combinatorial expression is new.

Multibarrier Collaborative Modulation Devices with Ultra-High Logic Operation Density.

The demands for highly miniaturized and multifunctional electronics are rapidly increasing. As scaling-down processes of transistors are restricted by physical limits, reconfigurable electronics with switchable operation functions for different tasks are developed for higher function integration based on split- or vertical-dual-gate structures. To promote the present reconfigurable electronics and exceed the function integration limit, the critical issue is to integrate complex operations into simple circuit forms by establishing more control dimensions. This work proposes a multibarrier collaborative (MBC) modulation architecture to increase the control dimension by multiple forms of potential barriers and achieves combinational and reconfigurable logic operations by a single MBC device. The MBC architecture exhibits ultrahigh logic operation density, including 58.8% area reduction for multiplexer operations and 71.4% area reduction for 4-logic reconfigurable operations. Besides, a hardware security module composed of 4 MBC devices implementing 8 types of logic operations is demonstrated. This work reveals an effective design of function integration for next-generation electronics.

Multi-Level Sum of Product (SOP) Network Power Optimization Based on Switching Graph

The article presents the methodology of optimization of technology mapping of a multi-output function implemented in the form of sum of product (SOP) networks. The optimization is based on the concept of reducing the switching activity of combinational circuits. The aim of reducing network switching is to limit the consumption of dynamic power. Since dynamic power is one of the components of the total power consumed by digital systems, this leads to an optimization focused on the energy efficiency of digital systems. The basis of the proposed method is the technology mapping using a modified output graph describing the result of minimizing the multi-output function. The modified output graph, in terms of parameters associated with dynamic power, is defined as a switching graph. It was assumed that the key parameter associated with dynamic power is the switching activity of individual nodes of the logic network. The article presents elements of switching graph optimization which lead to the improvement of parameters associated with the dynamic power of the circuit. The essence of the proposed optimization methods is the appropriate movement of products and connections occurring in the logic network. Reducing the number of logic network vertices is also extremely important. The effectiveness of the proposed method was confirmed by the results of experiments performed on selected benchmarks. A significant reduction in the total value of switching activity was obtained for the optimized structures.

Innovative Multi-Bit Test Pattern Generators with Variable LFSR Selection Mechanisms

Test Pattern Generators is an important module for testing Asynchronous circuits that guarantee fault detection. In this paper a multi-bit TPGs with tunable LFSR lengths is presented. Our method enables smooth transitions between various word lengths by dynamically selecting LFSR configurations based on control signals. For 4-bit to 7-bit combinational circuits, we have derived a polynomial-based LFSRs and shown effect of stuck-at-fault detections through extensive testing. It includes a discussion of instructional insights regarding fault coverage and digital circuit design. By bridging fixed and flexible BIST solutions, our adaptive TPG design improves fault detection capabilities.

Photo- and ionochromic N-acylated 2-(aminomethylene)benzo[b]thiophene-3(2H)-ones containing a terpyridine receptor

New photo- and ionochromic N-acylated 2-(aminomethylene)benzo[b]thiophen-3(2H)-ones containing a terpyridine receptor have been synthesized. They absorb in the visible region of the spectrum at 423–426 nm and exhibit emission at 463–468 nm. Their irradiation in acetonitrile with light of 436 nm leads to a multi-stage rearrangement, including Z/E isomerization about the CC bond, N → O migration of the acyl group and the formation of non-emissive O-acylated E-isomers, which were isolated preparatively. Their structure was established unambiguously by IR, 1H, 13C NMR spectroscopy and HR mass spectrometry. The reverse thermal reaction with O → N migration of the acyl group is catalyzed by acid catalysts. N-Acylated compounds in acetonitrile selectively form non-fluorescent complexes with Fe2+ cations, which is accompanied by the naked-eye effect with changing the color from yellow to maroon. A successful selective interaction with AcO− led to the restoration of the initial absorption and emission properties. Density functional theory (DFT)calculations at the M06-2X/def2-TZVP level with the PCM solvation method were used to explain the observed photoisomerizations and ionochromic transformations. The obtained compounds represent multifunctional on-off-on molecular switches of optical and fluorescent properties upon sequential exposure to light and H+ or sequential addition of Fe2+ and AcO− ions. A combinatorial logic gate was designed based on the basis of these switching properties.

COMPUTING THE DEGREE-4 INVARIANT POLYNOMIAL BASIS FOR 7 QUBITS

Understanding the complexity of entangled states within the context of SLOCC (stochastic local operations and classical communications) involving several number qubits is essential for advancing our knowledge of quantum systems. This complexity is often analyzed by classifying the states via local symmetry groups. Practically, tthe resulting classes can be distinguished using invariant polynomials, but the size of these polynomials grows rapidly. Hence, it is crucial to obtain the smallest possible invariants. In this short note, we compute the basis of invariant polynomials of 7 qubits of degree 4, which are the smallest degree invariants. We obtain these polynomials using the representation theory and algebraic combinatorics.

All-optical combinational logical units featuring fifth-order cascade

Modern computational technologies are increasingly encountering significant limitations, driving a shift towards alternative paradigms such as optical computing. In this study, we introduce novel all-optical combinational logic units based on diffractive neural networks (D2NNs), designed to perform high-order logical operations both efficiently and swiftly using only two modulation layers. This innovative design offers increased processing speed, improved energy efficiency, robust environmental stability, and high error tolerance, making it exceptionally well-suited for a broad spectrum of applications in optical computing and communications. By leveraging transfer learning, we successfully developed a fifth-order cascaded combinational logic circuit for practical information transmission system. Furthermore, we reveal a pioneering application of our device in Optical Time Division Multiplexing (OTDM), demonstrating its capability to manage high-speed data transfer seamlessly without the need for electronic conversion. Extensive simulations and experimental validations highlight the potential of our model as a foundational technology for future optical computing architectures, paving the way toward more sustainable and efficient optical data processing platforms.