CNTFET Model Research Articles

Design of Ternary and Quaternary Asynchronous Up/Down Counter using CNTFET

This paper presents designs of ternary and quaternary up/down counters of single and multiple digits using CNTFET. The proposed counters have a special feature of counting in dual mode; up counting and down counting which makes these designs distinct from other existing designs. The proposed counters are designed using ternary/quaternary D flip-flops and a dynamic successor-predecessor circuit. The D flip-flops are built using standard ternary/quaternary inverters (STI/SQI) with an additional reset feature. The proposed dynamic successor-predecessor circuit has the capability of acting either as a successor or as a predecessor circuit based on a control signal. Counter circuits of multiple digits have been achieved with the help of a few additional transistors along with the single-digit counter circuits. All the proposed designs have been simulated in HSPICE using Stanford University’s 32 nm CNTFET model and simulation results have been noted. When compared with existing designs, the proposed designs show improvements in power and energy efficiency.

Efficient 32-nm CNTFET-Based 1-Bit Adder: A Fast and Energy-Optimized Design

CNTFETs are a shows potential choice for traditional CMOS technology due to their potential for lesser power consumption and superior performance. In the present paper, a new 1-bit hybrid full adder has been deliberated and proposed using both pass transistor (PT) and transmission gate logics (TGL), which utilizes a total of 16 transistors. The combination of PT and TGL can lead to improved power efficiency, reduced delay, and enhanced circuit performance in various VLSI applications. For 0.9 V supply voltage at 32-nm CNTFET technology, the power consumption is 0.0748 μW, which is to be an exceptionally low value with a lesser delay of 7.586 Ps and the power-delay-product (PDP) of 0.5674 aJ. The results obtained from this analysis demonstrate the power efficiency, speed, and overall performance of the proposed full adder design. The combination of 32-nm CNTFET technology, deliberate circuit design choices, and the use of specific logic elements (CMOS inverters and strong transmission gates) contributes to the reported characteristics. Using a 0.9 V supply voltage and 32-nm Stanford CNTFET Model technology, the suggested 1-bit adder circuit's concert was investigated using the Mentor Graphics Tool. Finally, using the proposed 1-bit full adder circuit, an N-bit ripple carry adder (N=8, 16 & 32) is implemented and demonstrated. The Simulation results of the 8-bit RCA with a power consumption of 0.373 μW, the delay is 16.852 Ps and the PDP is 6.2857 aJ. These results show that proposed RCA’s have better performance compared to the already reported designs in terms of performance, speed, and power economy.

A CNTFET based stable, single-ended 7T SRAM cell with improved write operation

Many researchers are working to improve the write operation in SRAM bit-cell for better write stability, low power dissipation, and minimal access time during the write process. However, the read and hold operation parameters should not be compromised to achieve these improvements. This paper presents a stable single-ended seven-carbon nanotube field-effect transistor (CNTFET) driven SRAM cell with improved write operation. The one-side inverter weakening approach for write and transistor decoupling for read operation leads to reduced dynamic power, low write delay, reduced leakage power, and improved stability. The proposed design is compared with conventional 6T (Conv6T) and three recently proposed designs, i.e., feedback-cutting 8T (feed-cut 8T), Low-power 8T and low-leakage 7T cell. The write delay and write PDP of the proposed design improve by 4.05×/3.58×/1.19×/1.21×and 11.11×/24.71×/2.96×/3.32×, respectively, compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. Also, the read delay and read PDP of the proposed design improve by 1×/1.03×/1.72×/1.56× and 1×/1.03×/1.82×/1.77×, respectively, compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. The leakage power of the proposed design is reduced by 1.08×/1.84×/0.46×/0.72× compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. The noise margin of the proposed cell for hold/write/read operation is improved by 1.02×/1.05×/0.99×compared to the Conv6T design. The simulation was performed using Stanford University’s 32 nm CNTFET model on the cadence virtuoso platform.

Implementation of Taguchi Method in Improving the Logic Gates Performance based on Carbon Nanotube Field Effect Transistor Technology

The International Roadmap for Device and Systems (IRDS) 2022 has emphasized the potential of CNTFETs to replace CMOS technology. Therefore, the substitution of silicon with carbon nanotubes (CNTs) has the potential to open new possibilities for the semiconductor industry, due to their compact size and superior electrical properties. Thus, this project utilized Cadence Virtuoso software to develop an optimized CNTFET design using Taguchi method. In this design, the Taguchi method was implemented to determine the best combination of design parameter and material for optimum CNTFET performance. The design parameter and material that had been chosen were the diameter of carbon nanotube, dielectric material and oxide thickness. The optimized CNTFET model is implemented in circuit study to analyse the propagation delay and power consumption. Five circuits had been designed from the optimized CNTFET which are the inverter, AND, OR, NAND and NOR circuit. The Taguchi Optimization method resulted in significant reductions in the power- delay product (PDP) for all circuits examined, ranging from 7.9954% for the AND circuit to an exceptional 99.9622% for the inverter circuit. These findings highlight the potential for improved power efficiency and faster circuit operation when utilizing the Taguchi Optimization approach.

Design of CNTFET-Based Electronic Circuits: A Review

In this review, we present some designs of CNTFET-based circuits, already proposed by us, and critically examine them here. For some of these, we compare the performance of proposed circuits both in CNTFET and CMOS technology. For the CNTFET model, we use a compact, semi-empirical model, already proposed by us and briefly recalled, while, for the MOSFET model, we use the BSIM4 one of the ADS library. Moreover in some design examples, we compare our results with those obtained using the Stanford model. All simulations are carried out using the software advanced design system (ADS), which is compatible with the Verilog-A programming language.

Efficient design approaches to model CNTFET-based Ternary Schmitt Trigger circuits

Digital computation using radix three offers the benefit of increased information density with less power consumption due to reduced interconnect complexity. Hence this brief presents two architectures for ternary Schmitt trigger designs that are implemented by combining shifting literals, ternary inverters and decoder equivalents using carbon nanotube technology. In the first proposed design, Schmitt trigger hysteresis curves are realized using shifting literals i.e. successor and predecessor cells. The second proposed design employs ternary inverters and a decoder equivalent of intermediate logic level for the implementation. The experimental analysis involves the simulations that are conducted using HSPICE and the standard Stanford CNTFET model. Simulation results confirm that the proposed ternary Schmitt trigger designs outperform in terms of power consumption and power delay product(PDP), showcasing the power reduction average of 75% and PDP reduction average of 79% respectively in comparison to recent counterparts. Moreover, Monte Carlo simulations are conducted to verify the robust operation of proposed designs and lesser deviations are observed in performance parameters towards process variations.

Study of Power Gain Capability of CNTFET Power Amplifier in THz Frequency Range

In this paper we study the application of a single-CNTFET as power amplifier in the THz frequency range, using a CNTFET model, already proposed by us. We show that the device has, within stable condition, a Maximum Gain of at least 29 dB at frequencies below 30 GHz, decreasing to 20 dB at 800 GHz and reaching 18 dB at 1 THz. Through the analysis of a simple example, we show that it is possible to obtain a stable amplifier with tuned matching with a gain near the Maximum Gain at 1 THz. Finally we show that the matching of this device requires high ratio which could be hard to implement at 1 THz.

Study of CNTFETs as Memory Devices

In this paper we propose a procedure for the study of CNTFETs as memory devices. In particular we analyze the design of a 6-T SRAM, in order to evaluate the writing and reading times, in single and double supplies, the static noise margin, the static power consumption and the power-delay product. For these goals, we use a CNTFET model, already proposed by us. Then we apply the same procedure using the Stanford model in order to compare the obtained results. At last we apply the proposed analysis for the design of a 6-T SRAM in CMOS technology, showing the improvements obtained with CNTFET technology.

Analysis of a CS amplifier Based on CNTFET with parasitic elements of interconnection lines

In this paper we present a procedure to study the effects of parasitic elements (capacitances, inductances and resistances) of interconnection lines in integrated circuits where Carbon Nanotubes are embedded. In particular the Drain/Source pads dimensions of CNT are analysed, as well as the interconnection lines between a CNT and an appropriate load are sized. In order to estimate parasitic elements in CNTs embedded integrated circuits, we analyse 50 nm technology. Moreover it is also possible for predictions analysis on 10 nm and 3 nm technology. We apply the proposed procedure to the design of a Common-Source amplifier, using a CNTFET model already proposed by us. The frequency domain simulations, obtained using the ADS simulator, show how the parasitic elements limit the performances of CNTs. In particular we obtain that the -3 dB cutting frequency of the examined amplifier full of parasitic elements increases as technology decreases. Moreover we repeat the proposed simulations using SPICE, obtaining results practically coincident but with the Verilog-A implementation we have mainly a simulation run time much shorter and a software much more concise and clear than schemes using ABM blocks in SPICE.

Comparative Analysis of CNTFET Models through the Design of a Differential Amplifier

In this paper we compare simulation results on a differential pair circuit using a CNTFET model, already proposed by us, with the result obtained using Stanford model. We study the case of differential pair with differential input and single ended output as core of a 50 GHz amplifier for mm waves band. We consider the case of a CNTFET having a single CNT tube with indices (19,0) and 25 nm long. For this circuit we present result for its main parameters: gain, input impedance, output impedance, noise and distortion. Since the Stanford model includes fixed capacitance, for comparison we applied the same capacitance on our model. Since this capacitances dominate the high frequency cut, results are not much different, except for the lack of noise modelling in the Stanford model.

CNTFET-based design of ternary logic gates with interchangeable standard positive and negative ternary output

This paper presents a novel CNTFET based design of ternary logics gates where all three ternary logics including standard, positive and negative ternary logic (ST, PT and NT) outputs for each gate are obtained from one structure and are interchangeable through some control inputs. Ternary logic overpowers the conventional binary logic in simplicity and energy efficiency as it reduces number of interconnects and chip area. In this paper design of ternary inverter, buffer, NAND, AND, NOR, OR, XOR and XNOR gates are presented where a unique feature of conversion between ST, PT, NT logic through a single output is being introduced. Besides a single logic gate is designed for a particular logic function and its complement combining both ternary and binary logic gate design technique. The proposed designs utilize the unique property of CNTFET, such as assigning the required threshold voltage value of the FET by changing the diameter of the carbon nanotube (CNT) through its chiral vector values which is very useful in designing multiple- valued logic (here ternary logic). The proposed circuits are simulated using Synopsys HSPICE with 32 nm CNTFET model provided by Stanford University and in each case average power values and propagation delays are duly noted. The effects of variation in some process parameters like channel length, dielectric oxide thickness and number of carbon nanotubes also have been discussed.

Alternative Design Techniques of Quaternary Latch, Flip-Flops and Counters in Nanoelectronics

In present study, multi-threshold property was firstly utilized to design a new standard quaternary inverter (SQI), quaternary buffer, binary-to-quaternary converter (B2Q) and quaternary-to-binary converter (Q2B) using CNTFET. Then, quaternary Latch and Flip Flops as well as quaternary counter with different structures were designed for the first time, based on inverter, buffer and binary-to-quaternary converter. The proposed circuits comprised with each other. The results of simulations using HSPICE software and 32 nm Stanford library CNTFET model indicated accurate operation and high efficiency of the proposed circuits techniques in the literature .Also, the advantages and disadvantages of each design were identified and discussed. The results of simulation represent the improved 60% and 77% in PDP of Q2B and B2Q when compared to the state of the art work.

Novel low-complexity and energy-efficient fuzzy min and max circuits in nanoelectronics

Ultra-efficient fundamental fuzzy Min and Max circuits are proposed in this paper using 3 CNTFETs. These are much energy-efficient compared to the state-of-the-art previous designs of Min and Max circuits, which are vastly superior to other models. This is due to the lack of a direct current path (between the inputs and GND /VDD) and the low output resistance. The superiority of the proposed Min and Max Circuits are technically described and proved. At the next step, an applied circuit, the ternary half-adder is developed based on the proposed Min and Max circuits. In these suggestions, all parts of half-adder, successor, and predecessor circuits are introduced based on ternary gates. The simulation results, as obtained through extensive simulations using Synopsys HSPICE and the 32 nm Stanford comprehensive CNTFET model, demonstrate that proposed Min and Max circuits are 22 times (%95.5) and 38 times (%97.39) more energy-efficient with a 0.5fF load compared to the best previous work, respectively. Furthermore, the proposed half-adder is %39 more energy-efficient with a 0.5fF load, compared to the previous work.

A CNT based VCO with extremely low phase noise and wide frequency range for PLL application

AbstractVoltage controlled oscillators (VCOs) are used as key components in phase‐locked loop systems for generating stable oscillation signals. Since the digital electronics industry increasingly needs a faster operation, VCOs need to generate signals at higher frequencies. This paper presents a voltage controlled oscillator with a wide frequency range and very low phase noise by using carbon nanotube technology. The Stanford CNTFET model is implemented in Verilog‐A, and the proposed CNTFET VCO is simulated using ADS software. Simultaneous use of forward bulk biasing and an inductor yields a carbon nanotube oscillator with a frequency range of 6‐20 GHz and a phase noise of −123 dBc/Hz.

Darlington Based 8T CNTFET SRAM Cells with Low Power and Enhanced Write Stability

In this paper, a novel low power and high write margin Darlington based NCNTFET Darlington 8T SRAM cell is proposed. The power consumption of the proposed Darlington SRAM cell is compared with that of conventional 6T CNTFET and conventional 8T CNTFET SRAM cells. The power consumption of the proposed Darlington SRAM cells is very less as compared to that of conventional 6T and 8T CNTFET SRAM cells for all write, hold, and read operations. The write static noise margin (WSNM) of the proposed NCNTFET Darlington 8T cell is found to increase by 70.83% than that of both conventional 6T and 8T CNTFET SRAM cell. Effect of CNTFET parameters such as chiral vectors (m,n), gate oxide thickness (Hox), dielectric constant of gate oxide material (Kox), temperature, pitch value, number of carbon nano tubes (CNTs) and supply voltage (VDD), on the power performance, drain current (ID) and drain to source voltage (VDS) of the novel proposed Darlington SRAM cell are investigated. The write, hold, and read power consumption of proposed NCNTFET Darlington 8T SRAM cell is compared with that of some of the existing SRAM cells. The simulation is carried out using Stanford University 32 nm CNTFET model.

A Novel Darlington-Based 8T CNTFET SRAM Cell for Low Power Applications

The design of low power memory cells is the dream of engineers in memory design. A Darlington-based 8T CNTFET SRAM cell is suggested in this paper. It is called the proposed P_CNTFET Darlington 8T SRAM Cell. Compared with that of the traditional 6T and 8T CNTFET SRAM cells, the power and noise performances of the proposed SRAM cell are comparable. Compared to the traditional SRAM cells, the write, hold, read and dynamic power consumption of the proposed cell is much lower. The CNTFET parameters are optimized to boost the noise margin performance of the suggested bit cell. For optimized parameters, the power consumption and SNM of the proposed cell are compared with conventional cells. In contrast to the conventional cells, the HSNM and WSNM of the proposed cell are improved by 6.25% and 66.6%. The proposed cell’s RSNM is 38% greater than the traditional 6T SRAM cell. The proposed cell’s RSNM is 3.33% less than the traditional 8T SRAM cell. MOSFET is also used to implement the proposed SRAM cell and its noise margin and power performance are compared with traditional MOSFET-based SRAM cells. As with the conventional cells, the MOSFET-based implementation of the proposed cell power and SNM performance is also very good. The simulation is done with the HSPICE simulation tool using the Stanford University 32[Formula: see text]nm CNTFET model.

A ring oscillator with very low phase noise and wide frequency range using carbon nanotube technology for PLL applications

This paper presents a wide frequency range three-stage voltage-controlled ring oscillator in CNTFET technology. The advantages of CNTFETs are the high speed of charge carriers, high signal to noise ratio, small size and ballistic transport. Therefore in comparison with MOSFETs, they have a higher frequency, and can operate at a wide frequency range with a very low phase noise if forward bulk bias and active inductor techniques are simultaneously used in the oscillators that employ CNTFETs. In this paper, the Stanford CNTFET model is implemented in Verilog-A, and the proposed CNT ring oscillator is simulated using ADS software over the 50–500 GHz frequency range. The phase noise of the oscillator is − 136 dBc/Hz at 1 MHz offset, which is suitable for PLL applications.

Technique to Dynamically Reconfigure FPGAs using Control Registers

Due to increased use of FPGAs computation intensive applications, the need for embedded processing system integrated with programmable logic device has also increased. Configuration of programmable logic device by the processing system through its interface improves the efficiency of the device. In order to operate as a stand-alone device and to have a better efficiency, the programmable logic device must be capable of dynamically programming its own configuration memory. In this paper, we propose a configurable logic block with a control register to improve performance of the programmable logic device. The control register acts like a decentralized configuration memory array which can be programmed by other such configurable logic blocks. The FPGAs are fault tolerant devices with repetitive structures requiring high packaging density. This property of FPGA enables the use of CNTFETs for design of FPGAs. CNTFETs offer high trans-conductance and 1-D ballistic transport of electrons and holes which minimizes the power consumed by the FPGA. The proposed control register based architecture was implemented using Cadence Virtuoso using virtual source CNTFET model from Stanford University. A power reduction of 17.62% is achieved using CNTFETs when compared with FINFET at same technology node and the architecture was verified for various configurations of the control register.

Evaluation and Comparison of CMOS logic circuits with CNTFET

In this paper, a comparison between CMOS and MOSFET base circuits HSPICE is done with software. 0.13 CMOS transistor model for simulation and CNTFET Model of Stanford University used. In simulations amounts of power, circuit delay and PDP is calculated and these values were compared at the end. And tried to CNTFET applications of transistors in circuit design, including memory and logic circuits Ternary be expressed.

High Performance Robust Keeper Design Technique for Wide Fan-In Domino OR Logic Using CNTFET 16nm Node Technology

This paper deals with the proposed adaptable threshold keeper&dynamic buffer technique(ATKDB) for CNTFET based wide fan in domino OR logic which simultaneously reduces the average power and propagation delay of the wide fan in logic implementationcompared to various dominogatetopologies.The proposed technique provides adaptable threshold voltage for the keeper transistor by means of a designed body bias generator which drives thebulk of the keeper and there by regulates the power. The design also includes a dynamic buffer at the output node to reduce pre-charge phase power consumption. With this technique, threshold voltage for keeper device is varied dynamically to reduce the contention current and clock loading. The proposed system was tested for 16 and 32 input domino gate using 16nm CNTFET model andthesatisfactoryresults w.r.t power and delay wereobtained.