CMOS VLSI Process Research Articles

Real-Time Ultra-Low Power ECG Anomaly Detection Using an Event-Driven Neuromorphic Processor.

Accurate detection of pathological conditions in human subjects can be achieved through off-line analysis of recorded biological signals such as electrocardiograms (ECGs). However, human diagnosis is time-consuming and expensive, as it requires the time of medical professionals. This is especially inefficient when indicative patterns in the biological signals are infrequent. Moreover, patients with suspected pathologies are often monitored for extended periods, requiring the storage and examination of large amounts of non-pathological data, and entailing a difficult visual search task for diagnosing professionals. In this work we propose a compact and sub-mW low power neural processing system that can be used to perform on-line and real-time preliminary diagnosis of pathological conditions, to raise warnings for the existence of possible pathological conditions, or to trigger an off-line data recording system for further analysis by a medical professional. We apply the system to real-time classification of ECG data for distinguishing between healthy heartbeats and pathological rhythms. Multi-channel analog ECG traces are encoded as asynchronous streams of binary events and processed using a spiking recurrent neural network operated in a reservoir computing paradigm. An event-driven neuron output layer is then trained to recognize one of several pathologies. Finally, the filtered activity of this output layer is used to generate a binary trigger signal indicating the presence or absence of a pathological pattern. We validate the approach proposed using a Dynamic Neuromorphic Asynchronous Processor (DYNAP) chip, implemented using a standard 180nm CMOS VLSI process, and present experimental results measured from the chip.

WIDEBAND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORKS

This paper presents an analog VLSL circuit for implementation of Artificial Neural Networks (ANNs ). The building blocks of the proposed circuit include Differential voltage current controlled source (DVCCS), Super MOSFET and Differential voltage controlled voltage source (DVCVS) which are used to multiply incoming analog signals with variable weights, and current in / current out sigmoid function circuit. The proposed circuit can be easily implemented in a 0.34 μ m CMOS VLSI process. Simulations are presented to confirm the validity of the proposed circuit.

Micropower Circuits for Bidirectional Wireless Telemetry in Neural Recording Applications

State-of-the art neural recording systems require electronics allowing for transcutaneous, bidirectional data transfer. As these circuits will be implanted near the brain, they must be small and low power. We have developed micropower integrated circuits for recovering clock and data signals over a transcutaneous power link. The data recovery circuit produces a digital data signal from an ac power waveform that has been amplitude modulated. We have also developed an FM transmitter with the lowest power dissipation reported for biosignal telemetry. The FM transmitter consists of a low-noise biopotential amplifier and a voltage controlled oscillator used to transmit amplified neural signals at a frequency near 433 MHz. All circuits were fabricated in a standard 0.5-microm CMOS VLSI process. The resulting chip is powered through a wireless inductive link. The power consumption of the clock and data recovery circuits is measured to be 129 microW; the power consumption of the transmitter is measured to be 465 microW when using an external surface mount inductor. Using a parasitic antenna less than 2 mm long, a received power level was measured to be -59.73 dBm at a distance of one meter.

A silicon implementation of the fly's optomotor control system.

Flies are capable of stabilizing their body during free flight by using visual motion information to estimate self-rotation. We have built a hardware model of this optomotor control system in a standard CMOS VLSI process. The result is a small, low-power chip that receives input directly from the real world through on-board photoreceptors and generates motor commands in real time. The chip was tested under closed-loop conditions typically used for insect studies. The silicon system exhibited stable control sufficiently analogous to the biological system to allow for quantitative comparisons.

Bonded wafer substrates for integrated detector arrays

Bonded wafer substrates that are optimized for integrating high-energy-particle silicon detector arrays with their readout electronics have been fabricated. The detectors are processed in the handle wafer, which is a 300- mu m-thick, high-resistivity, <111> silicon wafer. This wafer is bonded to a primary wafer using a low-temperature process that does not affect the detector material. The support electronics are processed in the remnant of the primary wafer, which is a submicron-thick <100> silicon film formed by a bond-and-etchback procedure. These two materials are isolated from each other by a radiation-hardened dielectric film. The integration process is based on a low-temperature, radiation-hardened VLSI CMOS process that is also shown not to seriously affect the detector material.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Multibit oversampled Sigma Delta A/D converters as front end for CD players

A technique is presented for deriving all of the different control signals needed for focusing and radial tracking in a digital servosystem for compact disc (CD) players, as well as the full band data from the disc. Because of the different natures of all those signals, different bandwidth and dynamic range, complex analog anti-aliasing circuits, and several types of A/D (analog-to-digital) converters would normally be required to convert the signals from the analog to digital domain. With the proposed technique it is possible to carry out the conversion of the high-frequency data as well as the low-frequency control signals with only a single type of multibit sigma-delta ( Sigma Delta ) A/D converter in combination with digital signal processing. The use of Sigma Delta type A/D conversion also has other advantages such as its suitability for integration in a CMOS VLSI process and the fact that the requirements for the anti-aliasing filters in front of the converters are relaxed due to the oversampling technique. >

A VLSI demodulator for digital RF network applications: theory and results

An all-digital demodulator/detector which is suitable for both analog FM and digital phase/frequency modulations is presented. The system uses complex sampling, which employs a single A/D (analog/digital) converter to sample the signal at an intermediate frequency (IF) and produce baseband in-phase (I) and quadrature phase (Q) signals, and a simplified technique for reducing the effect of the I/Q timing misalignment usually associated with this approach. The system also includes two detectors which operate simultaneously to provide noncoherent and differentially coherent detection, as well as automatic gain control (AGC) and automatic frequency control (AFC). The flexibility afforded by the two concurrent detectors in this all-digital system is shown to make it suitable for a wide range of applications. The theory behind the demodulator/detector system is described, and an implementation using a 1.25- mu m bulk CMOS VLSI process is presented. Methods are shown for extending and improving the I/Q sampling misalignment correction technique, as well as for reducing the A/D sampling rate for a given IF frequency. Simulation and experimental results illustrate system performance for both analog and digital modulations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Time-multiplexed analogue circuit for implementing artificial neural networks

A time-multiplexed analogue circuit is described for implementing artificial neural networks. Important parameters can be programmed using external passive components and networks of arbitrary size and complexity can be constructed with no degradation in network performance. The proposed IC is suitable for implementation using a VLSI CMOS process.

Computation of steady-state CMOS latchup characteristics

Robust computational techniques are presented for steady-state characterization of CMOS latchup via numerical device simulation. Of specific interest are efficient means of accurately evaluating knees in I-V characteristics, corresponding to latchup triggering and holding points. Making use of predictor-corrector continuation procedures and special initial-guess strategies, more than an order of magnitude improvement in computational efficiency is achieved over previous approaches. It is shown that for some latchup problems, these methods are essential due to their unique ability to trace characteristics that are multivalued in both I and V. Simulated results for both triggering and holding characteristics of a VLSI CMOS process are presented, from which primary structural dependencies are identified and new physical insight is obtained. >

Characterization of Boron‐Implanted Silicon at Various Depths from the Surface by Raman Scattering

not Available.

Shallow source-drain structures for VLSI CMOS technology

This paper proposes an improved CMOS source-drain technique which employs amorphising silicon implants prior to dopant implantation to eliminate ion channelling and platinum silicidation to substantially reduce sheet resistance. Counterdoping of the p+ regions by high concentration arsenic implantation is used to enable both NMOS and PMOS devices to be manufactured with only one photolithographic masking operation. The technique has been incorporated into a VLSI CMOS process schedule at our laboratories.

The Formation of Shallow Low-Resistance Source-Drain Regions for VLSI CMOS Technologies

As a result of MOS device scaling, very shallow source-drain structures are needed to minimize short-channel effects in 1-/spl mu/m transistors. This can be readily achieved with highly doped arsenic regions for NMOS devices but is more difficult using boron for PMOS devices. In addition, shallow junctions suffer from inherently high sheet resistances due to dopant solid solubility limitations. This paper proposes an improved CMOS source-drain technology to overcome both these problems. The technique employs amorphizing silicon implants prior to dopant implantation to eliminate ion channeling and platinum silicidation to substantially reduce sheet resistance. Counterdoping of the p/sup +/ regions by high-concentration arsenic implantation is used to enable both NMOS and PMOS devices to be manufactured with only one photolithographic masking operation. Using this technique, n/sup +/ and p/sup +/ junction depths are 0.22 /spl mu/ and of 8 /spl Omega/sq. sheet resistance. By creating oxide sidewalls on gate conductors, polysilicon can be silicided simultaneously with diffusions. Results of extensive materials analysis are discussed in detail. The technique has been incorporated into a VLSI CMOS process schedule at our laboratories.

The formation of shallow low-resistance source—Drain regions for VLSI CMOS technologies

As a result of MOS device scaling, very shallow source-drain structures are needed to minimize short-channel effects in 1-µm transistors. This can be readily achieved with highly doped arsenic regions for NMOS devices but is more difficult using boron for PMOS devices. In addition, shallow junctions suffer from inherently high sheet resistances due to dopant solid solubility limitations. This paper proposes an improved CMOS source-drain technology to overcome both these problems. The technique employs amorphizing silicon implants prior to dopant implantation to eliminate ion channeling and platinum silicidation to substantially reduce sheet resistance. Counterdoping of the p+regions by high-concentration arsenic implantation is used to enable both NMOS and PMOS devices to be manufactured with only one photolithographic masking operation. Using this technique, n+and p+junction depths are 0.22 µm and of 8 Ω/sq. sheet resistance. By creating oxide sidewalls on gate conductors, polysilicon can be silicided simultaneously with diffusions. Results of extensive materials analysis are discussed in detail. The technique has been incorporated into a VLSI CMOS process schedule at our laboratories.

Improved bipolar transistor performance in a VLSI CMOS process

Bipolar n-p-n transistors have been successfully fabricated on a high-performance n-well VLSI CMOS process incorporating an additional mask and implant step. A double active-base implant was utilized to control the base surface concentration and the transistor characteristics separately. High forward common-emitter current gain and collector-emitter breakdown voltage can be achieved by this process. n-p-n transistors with β f = 100, BV CE0 = 9.0 V, and BV CB0 = 23 V can be easily fabricated on this scaled VLSI CMOS process.