Abstract
This paper proposes an improved CMOS source-drain technique which employs amorphising silicon implants prior to dopant implantation to eliminate ion channelling and platinum silicidation to substantially reduce sheet resistance. Counterdoping of the p+ regions by high concentration arsenic implantation is used to enable both NMOS and PMOS devices to be manufactured with only one photolithographic masking operation. The technique has been incorporated into a VLSI CMOS process schedule at our laboratories.
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