Computation of steady-state CMOS latchup characteristics

Abstract

Robust computational techniques are presented for steady-state characterization of CMOS latchup via numerical device simulation. Of specific interest are efficient means of accurately evaluating knees in I-V characteristics, corresponding to latchup triggering and holding points. Making use of predictor-corrector continuation procedures and special initial-guess strategies, more than an order of magnitude improvement in computational efficiency is achieved over previous approaches. It is shown that for some latchup problems, these methods are essential due to their unique ability to trace characteristics that are multivalued in both I and V. Simulated results for both triggering and holding characteristics of a VLSI CMOS process are presented, from which primary structural dependencies are identified and new physical insight is obtained. >