CMOS Single-photon Avalanche Diode Research Articles

A 3D photon-to-digital converter readout for low-power and large-area applications

A new trend in large area noble liquid experiments is to measure the scintillation light with photodetectors and their electronics inside the active volume. Compared to the typical approach of using silicon photomultipliers (SiPM) with an analog readout chain leading to an analog-to-digital converter, this paper presents a new 3D photon-to-digital converter (PDC) readout that takes advantage of the binary nature of the single-photon avalanche diodes (SPAD). The readout contains 4096 pixels over 25 mm2, each including a 3D bonding pad and a quenching circuit. The readout features three different outputs: a fast flag to get the timestamp of each event from an external time-to-digital converter, a digital sum to retrieve the number of pixels triggered during an event, and an analog monitor to generate an analog SiPM-like output. The analog monitor is also used to validate the two former digital outputs. The readout also includes 61 2D CMOS SPADs for validation purpose prior to the final 3D integration with SPADs custom made according to our design by Teledyne DALSA (Bromont, Canada). As a first system integration toward large-area detector applications, a mini-tile of 2 × 2 readouts has been developed to test all the functionalities. The measured single-photon timing resolution ranges from 72 to 93 ps FWHM across the mini-tile SPAD channels population (i.e. 4 × 61 channels). The flag timing resolution is below 95 ps RMS, which includes the contribution of the optimized flag H-tree but also an additional trigger tree that replaces the 3D SPAD array at this stage of development. Once bonded with the 3D SPADs, the trigger tree won't be required to measure the flag timing resolution. With the removed contribution of the trigger tree, the estimated flag timing resolution should be below 45 ps RMS. The extent of the benefits of the digital sum output depend on the application, and this paper focuses on two cases. First, a low-power coincidence scheme such as required by the nEXO liquid xenon experiment, leading to a power consumption as low as 140 μW per PDC. With a finer sampling of the scintillation light such as required for pulse shape discrimination in liquid argon, the power consumption remains below 100 μW per PDC. Overall, this readout is designed as a replacement for a typical analog SiPM chain, without compromise on the performances.

Effect of Proton Irradiation on Complementary Metal Oxide Semiconductor (CMOS) Single-Photon Avalanche Diodes

The effects of proton irradiation on CMOS Single-Photon Avalanche Diodes (SPADs) are investigated in this article. The I–V characteristics, dark count rate (DCR), and photon detection probability (PDP) of the CMOS SPADs were measured under 30 MeV and 52 MeV proton irradiations. Two types of SPAD, with and without shallow trench isolation (STI), were designed. According to the experimental results, the leakage current, breakdown voltage, and PDP did not change after irradiation at a DDD of 2.82 × 108 MeV/g, but the DCR increased significantly at five different higher voltages. The DCR increased by 506 cps at an excess voltage of 2 V and 10,846 cps at 10 V after 30 MeV proton irradiation. A γ irradiation was conducted with a TID of 10 krad (Si). The DCR after the γ irradiation increased from 256 cps to 336 cps at an excess voltage of 10 V. The comparison of the DCR after proton and γ-ray irradiation with two structures of SPAD indicates that the major increase in the DCR was due to the depletion region defects caused by proton displacement damage rather than the Si-SiO2 interface trap generated by ionization.

Effect of Proton Energy and Bias Conditions during Irradiation on CMOS Single-Photon Avalanche Diodes

Effect of Proton Energy and Bias Conditions during Irradiation on CMOS Single-Photon Avalanche Diodes

Pion Detection Using Single Photon Avalanche Diodes.

We present the first reported use of a CMOS-compatible single photon avalanche diode (SPAD) array for the detection of high-energy charged particles, specifically pions, using the Super Proton Synchrotron at CERN, the European Organization for Nuclear Research. The results confirm the detection of incident high-energy pions at 120 GeV, minimally ionizing, which complements the variety of ionizing radiation that can be detected with CMOS SPADs.

Multipoint Raman Spectrometer Based on a Time-Resolved CMOS SPAD Sensor

The potential of in-line Raman spectrometers for process monitoring applications has been shown for many industrial processes, but in most cases, only one measurement point has been monitored by one spectrometer. In this letter, we describe and demonstrate a novel, time-resolved method for measuring Raman spectra and fluorescence lifetimes from multiple points using a single excitation source and a single spectrometer. This technique is based on a combination of a time-resolved CMOS SPAD (single-photon avalanche diode) line sensor and a fitting optical light guiding system. The line sensor is designed to make multiple individual measurements at intervals of tens of nanoseconds and the optical light guiding system, in turn, produces matching temporal differences for optical signals from different measurement points. Thereby, signals from different points are distinguished in the time domain. A combined Raman and fluorescence lifetime monitoring of two measurement points was demonstrated with an oil-ethanol emulsion sample.

3-D Raman Imaging Using Time-Resolving CMOS SPAD Line Sensor and 2-D Mapping

The capability of Raman imaging to produce 2D and 3D chemical presentations of samples has gained a lot of interest in different application fields. In this paper, we present a 3D chemical image reconstruction based on 2D scanning of a sample utilizing a time-resolved Raman spectrometer based on a CMOS single-photon avalanche diode (SPAD) line sensor. The 2D scanning data contains the lateral information (XY-plane) whereas the time-of-arrival data of the Raman photons measured by the sensor carries the axial information (i.e., depth information, Z-axis). The sensor is fabricated in 110-nm CMOS technology. It has 256-spectral channels and each channel has its own 7-bit on-chip time-to-digital converter (TDC) with an adjustable resolution from 25 ps to 65 ps. In addition to the 3D chemical reconstruction of the scanned sample, we have also shown the ability to retrieve depth profiling information of each scanned pixel such as the boundaries and middle points of any selected layer over the depth range of the scanned object by means of a single measurement for each scanned pixel. In addition, we have discussed the system components and the post-processing parameters that affect the depth profiling accuracy and the 3D reconstruction operation the most. Results showed that the instrument response function of the system and the time gate window width in a post-processing phase are playing the most important role in determining the axial (depth) accuracy. We believe that our system will enable a whole new class of Raman applications that will allow simultaneous 3D chemical geometric representation at the cm-level during Raman operations.

CMOS SPAD Imager Array for Wide Radiation Temperature Sensing and Thermal Imaging

We have demonstrated a wide radiation temperature measurement by using a single-photon avalanche diode (SPAD) image array that is analogous to a silicon photomultiplier with a time-gating technique and an adjustable summed output. The detection temperature window ranging from 280 °C to 1050 °C can be achieved with a noise equivalent temperature difference (NETD) value of below 1 °C. The thermal image with a high detection rate up to 1680 Hz is obtained at the same detection temperature as a commercial CMOS thermal camera. We further demonstrate a thermal image with a spatial resolution of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$80~\mu \text{m}$ </tex-math></inline-formula> .

DCR and crosstalk characterization of a bi-layered 24 × 72 CMOS SPAD array for charged particle detection

This paper presents the results from the crosstalk and dark count rate (DCR) characterization of a 24 × 72 single photon avalanche diode (SPAD) array, fabricated in a 150 nm CMOS technology. The chip under test consists of a dual layer detection system developed in view of applications to charged particle tracking. A three step procedure, used for the crosstalk characterization, is presented. The crosstalk probability, taking place in 5 × 5 sub arrays built around noisy pixels, has been computed. Eventually, random telegraph signal (RTS) fluctuations in DCR, at different bias conditions, are briefly discussed.

High resolution TCSPC imaging of diffuse light with a one-dimensional SPAD array scanning system.

We report a time-correlated single-photon counting (TCSPC) imaging system based on a line-scanning architecture. The system benefits from the high fill-factor, active area, and large dimension of an advanced CMOS single-photon avalanche diode (SPAD) array line-sensor. A two-dimensional image is constructed using a moving mirror to scan the line-sensor field-of-view (FOV) across the target, to enable the efficient acquisition of a two-dimensional 0.26 Mpixel TCSPC image. We demonstrate the capabilities of the system for TCSPC imaging and locating objects obscured in scattering media - specifically to locate a series of discrete point sources of light along an optical fibre submerged in a highly scattering solution. We demonstrate that by selectively imaging using early arriving photons which have undergone less scattering than later arriving photons, our TCSPC imaging system is able to locate the position of discrete point sources of light than a non-time-resolved imaging system.

Smart Wide-field Fluorescence Lifetime Imaging System with CMOS Single-photon Avalanche Diode Arrays.

Wide-field fluorescence lifetime imaging (FLIM) is a promising technique for biomedical and clinic applications. Integrating with CMOS single-photon avalanche diode (SPAD) sensor arrays can lead to cheaper and portable real-time FLIM systems. However, the FLIM data obtained by such sensor systems often have sophisticated noise features. There is still a lack of fast tools to recover lifetime parameters from highly noise-corrupted fluorescence signals efficiently. This paper proposes a smart wide-field FLIM system containing a 192×128 COMS SPAD sensor and a field-programmable gate array (FPGA) embedded deep learning (DL) FLIM processor. The processor adopts a hardware-friendly and light-weighted neural network for fluorescence lifetime analysis, showing the advantages of high accuracy against noise, fast speed, and low power consumption. Experimental results demonstrate the proposed system's superior and robust performances, promising for many FLIM applications such as FLIM-guided clinical surgeries, cancer diagnosis, and biomedical imaging.

2-D Photon-Detection-Probability Simulation and a Novel Guard-Ring Design for Small CMOS Single-Photon Avalanche Diodes

CMOS single-photon avalanche diode (SPAD) array is a high-timing-resolution photon-counting image sensor. Pixel size shrinkage for high image resolution is highly desirable but hindered by the lowered photon-detection-probability (PDP) as the edge area becomes significant. We propose and demonstrate a parameter-free method for simulating PDP with the edge effect. Considering the doping profile, electric field, photon generation, and trigger probability distributions in two dimensions, the PDP reduction at the device edge is analyzed in a quantitative way. Besides, a novel guard-ring design for enhancing PDP of small SPAD has been proposed and simulated by our method. A threefold enhancement was obtained with the newly designed guard-ring structure compared with the original one. Our work is useful for developing small-pitch SPAD array for high-resolution imaging applications.

A Low-Noise CMOS SPAD Pixel With 12.1 Ps SPTR and 3 Ns Dead Time

Single-photon avalanche diodes (SPADs) have become the sensor of choice in many applications whenever high sensitivity, low noise, and sharp timing performance are required, simultaneously. Recently, SPADs designed in CMOS technology, have yielded moderately good performance in these parameters, but never equaling their counterparts fabricated in highly customized, non-standard technologies. The arguments in favor of CMOS-compatible SPADs were miniaturization, cost and scalability. In this paper, we present the first CMOS SPAD with performance comparable or better than that of the best custom SPADs, to date. The SPAD-based design, fully integrated in 180 nm CMOS technology, achieves a peak photon detection probability (PDP) of 55&#x0025; at 480 nm with a very broad spectrum spanning from near ultraviolet (NUV) to near infrared (NIR) and a normalized dark count rate (DCR) of 0.2 cps/<inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>m<inline-formula><tex-math notation="LaTeX">$^2$</tex-math></inline-formula>, both at 6 V of excess bias. Thanks to a dedicated CMOS pixel circuit front-end, an afterpulsing probability of about 0.1&#x0025; at a dead time of <inline-formula><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula>3 ns were achieved. We designed three SPADs with a diameter of 25, 50, and 100 <inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>m to study the impact of size on the timing jitter and to create a scaling law for SPADs. For these SPADs, a single-photon time resolution (SPTR) of 12.1 ps, 16 ps, and 27 ps (FWHM) was achieved at 6 V of excess bias, respectively. The SPADs operate in a wide range of temperatures, from &#x2212;65 <inline-formula><tex-math notation="LaTeX">$^{\circ }$</tex-math></inline-formula>C to 40 <inline-formula><tex-math notation="LaTeX">$^{\circ }$</tex-math></inline-formula>C, reaching a normalized DCR of 1.6 mcps/<inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>m<inline-formula><tex-math notation="LaTeX">$^2$</tex-math></inline-formula> at 6 V of excess bias for the 25 <inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>m at &#x2212;65 <inline-formula><tex-math notation="LaTeX">$^{\circ }$</tex-math></inline-formula>C. The proposed SPADs are ideal for a wide range of applications, including (quantum) LiDAR, super-resolution microscopy, quantum random number generators, quantum key distribution, fluorescence lifetime imaging, time-resolved Raman spectroscopy, to name a few. All these applications can take advantage of the vastly improved performance of our detectors, while enjoying the opportunities of megapixel resolutions promised by the economy of scale that is offered by CMOS technologies.

Architecture-Level Optimization on Digital Silicon Photomultipliers for Medical Imaging.

Silicon photomultipliers (SiPMs) are arrays of single-photon avalanche diodes (SPADs) connected in parallel. Analog silicon photomultipliers are built in custom technologies optimized for detection efficiency. Digital silicon photomultipliers are built in CMOS technology. Although CMOS SPADs are less sensitive, they can incorporate additional functionality at the sensor plane, which is required in some applications for an accurate detection in terms of energy, timestamp, and spatial location. This additional circuitry comprises active quenching and recharge circuits, pulse combining and counting logic, and a time-to-digital converter. This, together with the disconnection of defective SPADs, results in a reduction of the light-sensitive area. In addition, the pile-up of pulses, in space and in time, translates into additional efficiency losses that are inherent to digital SiPMs. The design of digital SiPMs must include some sort of optimization of the pixel architecture in order to maximize sensitivity. In this paper, we identify the most relevant variables that determine the influence of SPAD yield, fill factor loss, and spatial and temporal pile-up in the photon detection efficiency. An optimum of 8% is found for different pixel sizes. The potential benefits of molecular imaging of these optimized and small-sized pixels with independent timestamping capabilities are also analyzed.

Photon detection probability enhancement using an anti-reflection coating in CMOS-based SPADs.

This work presents a simulation and experimental study of the photon detection probability (PDP) enhancement in CMOS single-photon avalanche diodes (SPADs) using an anti-reflection coating (ARC) above the sensitive area. It is shown how the ARC layer can improve the PDP, not only by improving the optical transmission, but also by eliminating the penetration of the standing wave into a shallow region close to the silicon surface, where the multiplication region of the SPAD is formed. Furthermore, the appropriate ARC layer thickness corresponding to maximum PDP enhancement at different wavelengths over the visible spectrum is extracted to provide insight regarding the ARC selection if different ARC thicknesses are available within the CMOS process.

Certification of the efficient random number generation technique based on single‐photon detector arrays and time‐to‐digital converters

True random number generators (TRNGs) allow the generation of true random bit sequences, guaranteeing the unpredictability and perfect balancing of the generated values. TRNGs can be realised from the sampling of quantum phenomena, for instance, the detection of single photons. Here, a recently proposed technique, which implements a quantum random number generator (QRNG) out of a device that was realised for a different scope, is further analysed and certified [1]. The combination of a CMOS single-photon avalanche diode (SPAD) array, a high-resolution time-to-digital converter (TDC) implemented on a field programmable gate array (FPGA), the exploitation of a single-photon temporal degree of freedom, and an unbiased procedure provided by H. Zhou and J. Bruck [2, 3] allows the generation of true random bits with a high bitrate in a compact and easy-to-calibrate device. Indeed, the use of the ‘Zhou–Bruck’ method allows the removal of any correlation from the binary representation of decimal data. This perfectly fits with the usage of a device with non-idealities like SPAD's afterpulses, pixel cross-correlation, and time-to-digital converter non-uniform conversion. In this work, an in-depth analysis and certification of the technique presented in [1] is provided by processing the data with the NIST suite tests in order to prove the effectiveness and validity of this approach.

Experimental and simulation study of fill-factor enhancement using a virtual guard ring in n+/p-well CMOS single-photon avalanche diodes

The use of a physical guard ring in CMOS single-photon avalanche diodes (SPADs) based on n + /(deep)p-well and p + /(deep)n-well structures is a common solution to control the electric field of the SPADs periphery and prevent the premature lateral breakdown. However, this leads to a decrease of the detection efficiency, i.e., the fill-factor, especially when the SPADs size is reduced. Our paper presents an experimental and simulation study on replacing the physical guard ring by a virtual guard ring to improve the fill-factor and the scalability of a n + / p-well SPAD implemented in 0.35-μm pin-photodiode CMOS technology. Accordingly, the optimization of the virtual guard ring and its superiority at downscaling are discussed, and the SPAD scalability in size with respect to the fill-factor is quantified in this technology.

Dynamic fluorescence lifetime sensing with CMOS single-photon avalanche diode arrays and deep learning processors.

Measuring fluorescence lifetimes of fast-moving cells or particles have broad applications in biomedical sciences. This paper presents a dynamic fluorescence lifetime sensing (DFLS) system based on the time-correlated single-photon counting (TCSPC) principle. It integrates a CMOS 192 × 128 single-photon avalanche diode (SPAD) array, offering an enormous photon-counting throughput without pile-up effects. We also proposed a quantized convolutional neural network (QCNN) algorithm and designed a field-programmable gate array embedded processor for fluorescence lifetime determinations. The processor uses a simple architecture, showing unparallel advantages in accuracy, analysis speed, and power consumption. It can resolve fluorescence lifetimes against disturbing noise. We evaluated the DFLS system using fluorescence dyes and fluorophore-tagged microspheres. The system can effectively measure fluorescence lifetimes within a single exposure period of the SPAD sensor, paving the way for portable time-resolved devices and shows potential in various applications.

Investigation of random telegraph signal in two junction layouts of proton irradiated CMOS SPADs

This paper focuses on the understanding of the Random Telegraph Signal (RTS) in Single-Photon Avalanche Diodes (SPAD). We studied the RTS of two different SPAD layouts, designed and implemented in a 150-nm CMOS process, after proton irradiation. The two structures are characterized by different junction types: the first structure is constituted by a P+/Nwell junction, while the second is formed by a Pwell/Niso junction. RTS occurrence has been measured in about one thousand SPAD pixels and the differences addressed in two layouts are motivated and discussed. Hypotheses on the RTS origin are drawn by analyzing the RTS time constants and the RTS occurrence evolution as a function of the annealing temperature.

Towards combined quantum bit detection and spatial tracking using an arrayed single-photon sensor.

Experimental quantum key distribution through free-space channels requires accurate pointing-and-tracking to co-align telescopes for efficient transmission. The hardware requirements for the sender and receiver could be drastically reduced by combining the detection of quantum bits and spatial tracking signal using two-dimensional single-photon detector arrays. Here, we apply a two-dimensional CMOS single-photon avalanche diode detector array to measure and monitor the single-photon level interference of a free-space time-bin receiver interferometer while simultaneously tracking the spatial position of the single-photon level signal. We verify an angular field-of-view of 1.28° and demonstrate a post-processing technique to reduce background noise. The experimental results show a promising future for two-dimensional single-photon detectors in low-light level free-space communications, such as quantum communications.

Optical and Electrical Characterization and Modeling of Photon Detection Probability in CMOS Single-Photon Avalanche Diodes

Single-photon avalanche diodes (SPADs) are very attractive devices in optical detector applications where both CMOS integration and low light detection are critical. An important SPAD performance parameter is the photon detection probability (PDP) which has to be carefully characterized for the sensor design. In this article, we present a comprehensive modeling and experimental characterization of the PDP to obtain its optical and electrical dependency on different parameters including the wavelength and light incidence angle as well as the biasing condition. By calculating the optical absorption and the avalanche triggering probabilities within the silicon, the PDP of an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /p-well CMOS-implemented SPAD is accurately modeled. It is shown that due to the formation of a standing wave in different layers above the silicon, which significantly affects the optical transmission and the PDP spectrum, the application of the presented approach is necessary especially when an anti-reflection coating layer is not available. The obtained result shows an excellent agreement to our measurements and, therefore, the model can be reliably used for accurate design and optimization of SPAD-based detectors and to avoid very time-consuming experimental investigations, e. g. for obtaining the detector performance for deviations in the light incidence angle.