Abstract
Single-photon avalanche diodes (SPADs) have become the sensor of choice in many applications whenever high sensitivity, low noise, and sharp timing performance are required, simultaneously. Recently, SPADs designed in CMOS technology, have yielded moderately good performance in these parameters, but never equaling their counterparts fabricated in highly customized, non-standard technologies. The arguments in favor of CMOS-compatible SPADs were miniaturization, cost and scalability. In this paper, we present the first CMOS SPAD with performance comparable or better than that of the best custom SPADs, to date. The SPAD-based design, fully integrated in 180 nm CMOS technology, achieves a peak photon detection probability (PDP) of 55% at 480 nm with a very broad spectrum spanning from near ultraviolet (NUV) to near infrared (NIR) and a normalized dark count rate (DCR) of 0.2 cps/<inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>m<inline-formula><tex-math notation="LaTeX">$^2$</tex-math></inline-formula>, both at 6 V of excess bias. Thanks to a dedicated CMOS pixel circuit front-end, an afterpulsing probability of about 0.1% at a dead time of <inline-formula><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula>3 ns were achieved. We designed three SPADs with a diameter of 25, 50, and 100 <inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>m to study the impact of size on the timing jitter and to create a scaling law for SPADs. For these SPADs, a single-photon time resolution (SPTR) of 12.1 ps, 16 ps, and 27 ps (FWHM) was achieved at 6 V of excess bias, respectively. The SPADs operate in a wide range of temperatures, from −65 <inline-formula><tex-math notation="LaTeX">$^{\circ }$</tex-math></inline-formula>C to 40 <inline-formula><tex-math notation="LaTeX">$^{\circ }$</tex-math></inline-formula>C, reaching a normalized DCR of 1.6 mcps/<inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>m<inline-formula><tex-math notation="LaTeX">$^2$</tex-math></inline-formula> at 6 V of excess bias for the 25 <inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>m at −65 <inline-formula><tex-math notation="LaTeX">$^{\circ }$</tex-math></inline-formula>C. The proposed SPADs are ideal for a wide range of applications, including (quantum) LiDAR, super-resolution microscopy, quantum random number generators, quantum key distribution, fluorescence lifetime imaging, time-resolved Raman spectroscopy, to name a few. All these applications can take advantage of the vastly improved performance of our detectors, while enjoying the opportunities of megapixel resolutions promised by the economy of scale that is offered by CMOS technologies.
Highlights
S ILICON-BASED Single-photon avalanche diodes (SPADs) attracted increasing interest in the last decades thanks to their interesting performance [1], [2]
Where η is a light ratio computed during the calibration phase measuring the light power at the integrating sphere output port and at the location of the device under test (DUT) with a calibrated reference photodiode; S is the number of pulses at the SPAD output when exposed to light; ASP AD is the active area of the SPAD; FP D(λ) is the photon flux detected by the reference photodiode
We report on the design and characterization of a new SPAD fabricated in 180 nm CMOS technology, exhibiting a performance comparable or better than that of the most advanced custom SPADs, to date
Summary
S ILICON-BASED Single-photon avalanche diodes (SPADs) attracted increasing interest in the last decades thanks to their interesting performance [1], [2]. The circuits used for the SPAD front-end interface have been substantially improved over time, allowing the implementation of much more complex systems that fit a wider spectrum of applications [26]–[30] In this context, very large array sizes, up to 1Mpixel have been achieved [31], [32]. We present three SPAD pixel detectors, based on high-performance SPAD pixels implemented in 180 nm CMOS technology This device is designed to achieve high performance in terms of count rate, sensitivity, timing precision, noise, and power consumption. The latter is very important if the same architecture is implemented in large arrays.
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