CMOS Reliability Research Articles

Investigation of CMOS reliability in 28 nm through BTI and HCI extraction

The reduction in transistor size in commercial electronic circuits has been enabled by the use of new materials in the gate oxide. Assessing the reliability of 28 nm CMOS makes sense and is necessary for industrial purpose, especially for long-term use in extreme environments. Without the support of the manufacturer and to meet our typical requirements, we perform an ageing test for up to 16 months (12,000h), as opposed to the typical test performed for less than 1000 h, on 45 FPGA. Ageing drifts are monitored using 192 ring oscillators integrated in each FPGA and the measurement circuits are located inside the tested devices. To imply the negative effect of BTI and HCI, several combined stress conditions were applied: from negative to hot temperature, core voltages, stress frequencies and duty cycles. The raw data is correlated to external conditions during the measurement to compensate for them. The final goal is to obtain consistent data with limited bias. Therefore, we correctly extract the BTI and HCI drifts. The drifts of the BTI mechanism are modeled as a function of the duty cycle stress conditions. The dispersion of the data is then analyzed and a precise statistical approach leads us to a realistic estimate of its reliability. Degradations at low temperature are correlated with the number of switching, which suggests that the HCI is involved. Finally, we show than these degradations remain very low and thus quite compatible with an industrial application.

CMOS Reliability From Past to Future: A Survey of Requirements, Trends, and Prediction Methods

CMOS Reliability From Past to Future: A Survey of Requirements, Trends, and Prediction Methods

Flexible Setup for the Measurement of CMOS Time-Dependent Variability With Array-Based Integrated Circuits

This paper presents an innovative and automated measurement setup for the characterization of variability effects in CMOS transistors using array-based integrated circuits (ICs), through which a better understanding of CMOS reliability could be attained. This setup addresses the issues that come with the need for a trustworthy statistical characterization of these effects: testing a very large number of devices accurately but, also, in a timely manner. The setup consists of software and hardware components that provide a user-friendly interface to perform the statistical characterization of CMOS transistors. Five different electrical tests, comprehending time-zero and time-dependent variability effects, can be carried out. Test preparation is, with the described setup, reduced to a few seconds. Moreover, smart parallelization techniques allow reducing the typically time-consuming aging characterization from months to days or even hours. The scope of this paper thus encompasses the methodology and practice of measurement of CMOS time-dependent variability, as well as the development of appropriate measurement systems and components used in efficiently generating and acquiring the necessary electrical signals.

A Low-Overhead Integrated Aging and SEU Sensor

Aging has become a critical CMOS reliability issue in nanoscales. In general, the aging effect is exhibited as an increase in the delay of the combinational parts and robustness degradation of memory structures. To monitor the aging state of the combinational parts, this paper proposes an aging sensor that is combined with the flip-flops of a chip. The function of this sensor is based on monitoring the stability violation of the critical path output, before the rising edge of the clock signal. The precision of the proposed sensor is about $2.7 \times $ of the most accurate previously presented aging sensors. This is achieved by almost 33% less area overhead compared with state-of-the-art aging sensors. Furthermore, the presented sensor can detect and correct half of the single event upsets (SEUs), which lead to a bit-flip in the flip-flop. In addition, by utilizing the SEU detection circuitry, a scheme for reducing bias temperature instability, the most important aging process in the memory structures, is presented by balancing the duty cycle of the flip-flop transistors with negligible extra overhead.

On the Design and Analysis of Reliable RRAM-CMOS Hybrid Circuits

Resistive switching memories (RRAMs) are one of the most promising alternatives for nonvolatile storage and nonconventional computing systems. However, their behavior, and therefore their reliability, is limited by technology intrinsic constraints. Standard CMOS reliability analyses do not take into account RRAM-related misbehaviors. Consequently, new and more thorough characterization approaches are needed. Even more important, as RRAM is proposed to become a key piece in aerospace solutions, new radiation and temperature analyses should also be considered in reliability-oriented methodologies. This work presents a solution that completely characterizes RRAM and CMOS hybrid circuits under the combined effects of both technology and environmental error sources. The analysis strategy is based on three pillars: the definition of suitable models, the application of user-defined metrics to measure both circuit reliability and performance, and the efficient definition of the design space. These concepts are used by a powerful simulation framework, achieving automatic characterization of RRAM-based circuits by simultaneously considering multiple error sources. As a case of study, a thorough analysis of an RRAM read driver, including RRAM lifetime, circuit temperature, CMOS and RRAM variability, and radiation—both accumulated dose and single particle impacts—highlights the proposed approach capabilities.

Bias Temperature Instability Mitigation via Adaptive Cache Size Management

Bias temperature instability (BTI) is one of the major CMOS reliability issues in nanoscales. The main impact of BTI on SRAM memory cells is the degradation of the static noise margin (SNM), which leads to a higher susceptibility to failures. A variety of techniques for mitigating the impact of BTI on caches have been proposed at architecture level. However, their considerable overheads limit the application of such techniques. Recent studies showed that the utilization of the cache capacity widely varies from one workload to another and even within a workload. When cache utilization is low, for the majority of the cells, the same value is stored for a very long period, which significantly degrades SNM due to BTI. In this paper, we propose a technique to dynamically adjust the cache size according to the running workload cache requirement by monitoring the cache miss rate. The unused cache capacity is power gated to increase the energy efficiency and mitigate aging of the entire cache. The experimental results show that the proposed technique reduces hold and read SNM degradation by up to 48.1% and 33.3%, respectively, at the cost of 2.0% performance penalty.

Compact failure modeling for devices subject to electrostatic discharge stresses – A review pertinent to CMOS reliability simulation

This paper reviews the physical mechanisms and compact modeling approaches of two physical damages in MOS devices induced by electrostatic discharge (ESD) stresses; namely gate oxide breakdown and thermal failures. Theories underlying the failure mechanism are discussed and compact models that can be used to monitor ESD induced gate oxide breakdown and thermal failure are developed. Related work reported in the literature is discussed, and benchmarking of measurement data versus simulation results are included in support of the modeling work.

Introduction to Ion Channels and Disease

ADVERTISEMENT RETURN TO ISSUEEditorialNEXTIntroduction to Ion Channels and DiseaseJohn J. KasianowiczView Author Information National Institute of Standards and Technology, Physical Measurement Laboratory, Semiconductor and Dimensional Metrology Division, CMOS Reliability & Advanced Devices Group, Gaithersburg, Maryland 20899, United StatesCite this: Chem. Rev. 2012, 112, 12, 6215–6217Publication Date (Web):December 12, 2012Publication History Published online12 December 2012Published inissue 12 December 2012https://doi.org/10.1021/cr300444kCopyright © 2012 American Chemical SocietyRIGHTS & PERMISSIONSArticle Views3545Altmetric-Citations20LEARN ABOUT THESE METRICSArticle Views are the COUNTER-compliant sum of full text article downloads since November 2008 (both PDF and HTML) across all institutions and individuals. These metrics are regularly updated to reflect usage leading up to the last few days.Citations are the number of other articles citing this article, calculated by Crossref and updated daily. Find more information about Crossref citation counts.The Altmetric Attention Score is a quantitative measure of the attention that a research article has received online. Clicking on the donut icon will load a page at altmetric.com with additional details about the score and the social media presence for the given article. Find more information on the Altmetric Attention Score and how the score is calculated. Share Add toView InAdd Full Text with ReferenceAdd Description ExportRISCitationCitation and abstractCitation and referencesMore Options Share onFacebookTwitterWechatLinked InReddit PDF (985 KB) Get e-AlertsSUBJECTS:Anatomy,Ions,Molecular structure,Protein structure Get e-Alerts

A Simulation Study of Colpitts Oscillator Reliability and Variability

Nanoscale CMOS reliability and process variation effect on the LC Colpitts oscillator has been examined. Mixed-mode device and circuit simulation is used to investigate the physical insight of impact ionization to the Colpitts oscillator. An analytical equation of phase noise as a function of offset frequency, transistor parameters, and body bias has been derived. The analytical predictions are in good agreement with ADS simulation results. An adaptive body bias to minimize process variation effect on the Colpitts oscillator has also been proposed. The adaptive body bias technique effectively reduces the hot electron effect and process variability on the Colpitts oscillator performance, as supported by Monte Carlo simulation results.

Impact of SOI Thickness on FUSI-Gate CESL CMOS Performance and Reliability

The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided (FUSI)-metal-gate silicon-on-insulator (SOI) MOSFETs is investigated. High strain from a contact etch stop layer (CESL) in FUSI-gate transistors increases channel mobility and drain current driving. A CESL nMOSFET with a thick SOI demonstrates increased hot-electron degradation than its thin SOI counterpart. However, a ring oscillator using thick SOI transistors shows less gate delay due to enhanced drain current. Strained p-channel transistors with a large SOI thickness are more vulnerable to negative bias temperature instability. The oxide trap charge also plays an important role in the circuit performance degradation of RF low-noise and power amplifiers.

CMOS RF Power Amplifier Variability and Reliability Resilient Biasing Design and Analysis

This paper presents a novel biasing design that makes the complementary metal-oxide-semiconductor radio frequency power amplifier (PA) resilient to process variability and device reliability. The biasing scheme provides resilience through the threshold voltage adjustment, and at the mean time, it does not degrade the PA performance. Analytical equations are derived for studying the resilient biasing on PA process sensitivity. A class-AB PA with a resilient design is compared with a PA without such a design using a Predictive Technology Model 65-nm technology. The Advanced Design System simulation results show that the resilient biasing design helps improve the robustness of the PA in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> , <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> , and power-added efficiency. Except for postfabrication calibration capability, the adaptive body biasing design reduces the impact of variability and reliability on PA significantly when subjected to threshold voltage shift and electron mobility degradation.

High Temperature CMOS Reliability and Drift

Quartzdyne precision pressure transducers are required to continuously operate at 200°C for more than 5 years (&amp;gt;1 year at 225°C). Future electronics are targeted for 250°C operation. The current transducer electronics are based on 3 custom ASICs; an Oscillator, Voltage Regulator and a Frequency counter. Understanding custom integrated circuit component drift and interconnect life at temperature is crucial for the next generation of sensor applications. In this study, basic components are aged under bias at 225°C, 250°C and 275°C. Components include P-FET transistors, polysilicon resistors, and a diode connected PNP transistor. Measured parameter drift versus temperature and electrical stress is used to estimate device drift over time. Measured voltage regulator drift is compared with estimated drift based on resistor and diode measurements. Standard aluminum circuit interconnect life is measured at 3 current densities and temperatures. A modified current density guide is derived from Black's equation. Measured circuit interconnect life is shown to increase when diffusion barriers are present. Powered Quartzdyne hybrid circuit life results at 225°C are compared to expected lifetimes.

Some issues in advanced CMOS gate stack performance and reliability

This paper summarizes and analyzes some of our previous works on the advanced gate stacks for CMOS transistors focused on the following two topics: 1. Frequency dependence of Dynamic Bias Temperature Instability (DBTI) and the transistor degradation mechanism, 2. A novel way for metal gate Effective Work Function (EWF) modulation by incorporation of lanthanum elements in HfO 2 gate dielectric.

RF CMOS reliability simulations

We present a simulation approach to assess the reliability of an RF CMOS circuit under user conditions, based on existing DC degradation models for gate-oxide breakdown and hot-carrier degradation. The simulator allows for lifetime prediction of circuits that can withstand multiple breakdown events. Simulation results show that three power amplifiers with comparable initial circuit performance show an astronomic difference in reliability. The tool thus proves to be an asset in the analog design process.

SILC and NBTI in pMOSFETs With Ultrathin SiON Gate Dielectrics

Degradation of pMOSFETs under negative gate bias stress has been intensively studied, bearing in mind the macroscopic and phenomenological similarity between stress-induced leakage current (SILC) and negative bias temperature instability (NBTI). By investigating the electrical characteristics of small-size pMOSFETs, the microscopic mechanisms of the degradation have been vividly revealed. In particular 1) NBTI-induced positive charge generation leading to a decrease in gate hole current and 2) some kind of leak path formation giving rise to SILC are found to occur in parallel, but not simultaneously. This finding enables us to conclude that SILC and NBTI in pMOS are not linked directly at least from the microscopic perspective despite their macroscopic similarity. These results have brought about new insights into the degradation of pMOS under negative gate bias, which is now quite important to CMOS reliability

Probing negative bias temperature instability using a continuum numerical framework: Physics to real world operation

CMOS reliability is facing unprecedented challenges due to the continued scaling of device dimensions. To sustain the current scaling trends, it is imperative to understand the fundamental physics of failure mechanisms. Due to the inherent complexity of these mechanisms, some of the key failure mechanisms can be understood only by a numerical modeling approach. Most failure mechanisms have a characteristic time dependence to failure. Hence in this work, we use a numerical approach to investigate the time dependence of failure mechanism associated with interfacial kinetics at the Si/SiO 2 interface. Several models are critically examined to develop a reaction/diffusion based modeling framework for predicting interface state generation. Our modeling shows reactions at the Si/SiO 2 interface have a direct impact on the time dependence (or time slopes). These time kinetics predictions shed light on the underlying mechanisms behind an technologically important failure mechanism (negative bias temperature instability (NBTI)). In particular, the breaking of an interface SiH bond to release atomic H results in a time slope of 0.25, whereas the release of molecular H 2 results in a time slope of 0.165. Based on this model, we conclude NBTI degradation is dominated by diffusion of neutral molecular hydrogen defects. These models are extended to 2D simulations to study device layout effects. Our simulations suggest differences with device structure (Lgate, Width etc.) and agree with observed experimental results. The developed models are further applied to understand operation under dynamic and static stress.

CMOS reliability issues for emerging cryogenic Lunar electronics applications

We investigate the reliability issues associated with the application of CMOS devices contained within an advanced SiGe HBT BiCMOS technology to emerging cryogenic space electronics (e.g., down to 43 K, for Lunar missions). Reduced temperature operation improves CMOS device performance (e.g., transconductance, carrier mobility, subthreshold swing, and output current drive), as expected. However, operation at cryogenic temperatures also causes serious device reliability concerns, since it aggravates hot-carrier effects, effectively decreasing the inferred device lifetime significantly, especially at short gate lengths. In the paper, hot-carrier effects are demonstrated to be a stronger function of the device gate length than the temperature, suggesting that significant trade-offs between the gate length and the operational temperature must be made in order to ensure safe and reliable operation over typical projected mission lifetimes in these hostile environments.

Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study

A CMOS ring oscillator circuit is observed to operate even after a number of its FET's have undergone a hard gate oxide breakdown. The first breakdown is identified with emission microscopy and statistical tools to most likely occur in the circuit's nFET's. A physical model and an equivalent electrical circuit for an nFET after hard gate oxide breakdown are constructed and used to confirm the understanding of the impact of FET gate oxide breakdown on the ring oscillator. The observations are generalized to conclude that, provided stable soft breakdowns are the only gate oxide failures occurring at operating conditions, large parts of digital CMOS circuits will be unaffected by these failures.

RF CMOS Reliability

In this chapter the effects of hot carrier on the reliability of NMOS transistors are investigated. First, it is explained why the hot carrier issue can be important in RF CMOS circuits. Important mechanisms of hot carrier generation are reviewed and some of the techniques used in the measurement of hot carrier damages are explained. Next, results of measurement of DC hot carrier stress on the NMOS transistors are presented. The main focus here is the RF performance of the NMOS devices and circuits mode of them, but DC parameters of the device such as its I-V characteristics and threshold voltage are presented, as they directly affect the RF performance. Finally, using the measurements of hot carrier effects on single NMOS transistors, the effects of hot carriers on three parameters of a low noise amplifier, matching, power gain and stability, are predicted using circuit simulation.

Comparison of Device Performance Fabricated on Thick So and Bulk Wafers

AbstractWe have investigated the surface quality of thick 10μm Silicon-On-Insulator (SOI) wafers by comparing CMOS device performance and reliability of SOI wafers with those of bulk wafers. Large scale CMOS circuits, microcontrollers with 12Kbyte ROM and 512byte EEPROM, were fabricated on thick SOI wafers and on bulk wafers, and device performance and reliability were evaluated by means of functional tests and acceleration tests. A significant difference was observed only in the ROM bit-map failure analysis in the functional tests, in which the number of single bit failures (defined as a chain of up to 4 adjacent bit failures) was more evident on ROM fabricated on the thick SOI than that fabricated on bulk wafers. The result indicates that the crystal defects introduced by the initial oxygen concentration and excess film stress of the SiO interlayer may cause single bit failures. The SOI wafers were prepared by Direct Wafer Bonding 2(DWB) and a mechanical polishing technique to form a 10μm active silicon layer and a 625μm silicon substrate, which sandwiches a 0.25μm SiO2 interlayer. Thick SOI wafers such as these are becoming a promising material for one-chip integration of CMOS devices and Micro Electrical Mechanical System (MEMS) devices.