Investigation of CMOS reliability in 28 nm through BTI and HCI extraction

Abstract

The reduction in transistor size in commercial electronic circuits has been enabled by the use of new materials in the gate oxide. Assessing the reliability of 28 nm CMOS makes sense and is necessary for industrial purpose, especially for long-term use in extreme environments. Without the support of the manufacturer and to meet our typical requirements, we perform an ageing test for up to 16 months (12,000h), as opposed to the typical test performed for less than 1000 h, on 45 FPGA. Ageing drifts are monitored using 192 ring oscillators integrated in each FPGA and the measurement circuits are located inside the tested devices. To imply the negative effect of BTI and HCI, several combined stress conditions were applied: from negative to hot temperature, core voltages, stress frequencies and duty cycles. The raw data is correlated to external conditions during the measurement to compensate for them. The final goal is to obtain consistent data with limited bias. Therefore, we correctly extract the BTI and HCI drifts. The drifts of the BTI mechanism are modeled as a function of the duty cycle stress conditions. The dispersion of the data is then analyzed and a precise statistical approach leads us to a realistic estimate of its reliability. Degradations at low temperature are correlated with the number of switching, which suggests that the HCI is involved. Finally, we show than these degradations remain very low and thus quite compatible with an industrial application.